Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In video encoding and decoding, multiple partition blocks are generated by splitting a target block. A prediction mode is derived for at least a part of the multiple partition blocks, among the multiple partition blocks, and prediction is performed on the multiple partition blocks based on the derived prediction mode. When prediction is performed on the partition blocks, information related to the target block may be used, and information related to an additional partition block, which is predicted prior to the partition block, may be used.

Abstract: Disclosed are a method for inducing a prediction motion vector and an apparatus using the same. An image decoding method can include: a step of determining the information related to a plurality of spatial candidate prediction motion vectors from peripheral predicted blocks of a predicted target block; and a step of determining the information related to temporal candidate prediction motion vectors on the basis of the information related to the plurality of spatial candidate prediction motion vectors. Accordingly, the present invention can reduce complexity and can enhance coding efficiency when inducing the optimum prediction motion vector.

Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In video encoding and decoding, multiple partition blocks are generated by splitting a target block. A prediction mode is derived for at least a part of the multiple partition blocks, among the multiple partition blocks, and prediction is performed on the multiple partition blocks based on the derived prediction mode. When prediction is performed on the partition blocks, information related to the target block may be used, and information related to an additional partition block, which is predicted prior to the partition block, may be used.

Abstract: A high voltage transistor that includes a substrate where an active region is defined, a first impurity region and a second impurity region in the active region and a third impurity region between the first and second impurity regions, and a first gate electrode on the active region between the first impurity region and the third impurity region and a second gate electrode on the active region between the second impurity region and the third impurity region.

Abstract: A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.

Abstract: The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled.

Abstract: A high voltage transistor that includes a substrate where an active region is defined, a first impurity region and a second impurity region in the active region and a third impurity region between the first and second impurity regions, and a first gate electrode on the active region between the first impurity region and the third impurity region and a second gate electrode on the active region between the second impurity region and the third impurity region.

Abstract: A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.

Abstract: The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled.

Abstract: A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.

Abstract: A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region. Cell gate patterns are formed in the cell array region, and peripheral gate patterns are formed in the peripheral circuit region. Each of the cell gate patterns includes a control gate pattern and a capping pattern, and each of the peripheral gate patterns has a smaller thickness than the cell gate pattern. An interlayer dielectric layer is formed on the resultant structure having the cell gate patterns and the peripheral gate patterns. The interlayer dielectric layer is planarized by etching until the top surface of the capping pattern is exposed, so that an interlayer dielectric pattern is formed. The interlayer dielectric pattern covers the peripheral circuit region and fills a space between the cell gate patterns.

Abstract: An electrically erasable programmable read-only memory (EEPROM) device includes an EEPROM cell located on a semiconductor substrate, the EEPROM cell including a memory transistor and a selection transistor. A source region and a drain region are located on the semiconductor substrate adjacent to opposite sides of the EEPROM cell, respectively, and a floating region is positioned between the memory transistor and the selection transistor. The source region includes a first doped region, a second doped region and a third doped region, where the first doped region surrounds a bottom surface and sidewalls of the second doped region, and the second doped surrounds a bottom surface and sidewalls of the third doped region. Also, a second impurity concentration of the second doped region is higher than that of the first doped region and lower than that of the third doped region.

Abstract: A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.

Abstract: A method for coding a mask read-only memory (ROM) implants impurity ions into a semiconductor substrate so as to form a first impurity region, and forms a plurality of gate electrodes on the semiconductor substrate. Next, sidewalls on both sides of each of the gate electrodes are formed, and source and drain impurity regions are formed in the semiconductor substrate at respective sides of each of the gate electrodes. Then a mask over the semiconductor substrate, which exposes at least one of the gate electrodes and which exposes the source and drain impurity regions associated with the exposed gate electrode, is formed, and code ions are implanted into the semiconductor substrate. The semiconductor substrate is also annealed so that the source and drain impurity regions associated with the exposed gate electrode electrically contact the first impurity region.