Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes: a gate stack structure including a plurality of interlayer insulating layers and a plurality of conductive patterns, which are alternately stacked in a vertical direction; a dummy stack structure including a plurality of dummy interlayer insulating layers and a plurality of sacrificial layers, which are alternately stacked in the vertical direction, the dummy stack structure being disposed at a level at which the gate stack structure is disposed; a channel structure penetrating the gate stack structure; a memory layer disposed between each of the plurality of conductive patterns and the channel structure; and a dummy pillar penetrating a portion of the dummy stack structure with a length less than a length of the channel structure in the vertical direction.

Abstract: Provided is a metal interconnection structure of a semiconductor device, including a first metal film pattern disposed on an upper part of an insulation film of a semiconductor substrate; an intermetallic dielectric film having a metal contact plug in which a barrier layer, a metal film for contact plug and a second metal film are sequentially disposed, on the first metal film pattern; and a second metal film pattern disposed on the metal contact plug and intermetallic dielectric film and connected to the metal contact plug.

Abstract: Provided is a metal interconnection structure of a semiconductor device, including a first metal film pattern disposed on an upper part of an insulation film of a semiconductor substrate; an intermetallic dielectric film having a metal contact plug in which a barrier layer, a metal film for contact plug and a second metal film are sequentially disposed, on the first metal film pattern; and a second metal film pattern disposed on the metal contact plug and intermetallic dielectric film and connected to the metal contact plug.

Abstract: Provided is a metal interconnection structure of a semiconductor device, including a first metal film pattern disposed on an upper part of an insulation film of a semiconductor substrate; an intermetallic dielectric film having a metal contact plug in which a barrier layer, a metal film for contact plug and a second metal film are sequentially disposed, on the first metal film pattern; and a second metal film pattern disposed on the metal contact plug and intermetallic dielectric film and connected to the metal contact plug.

Abstract: Provided is a metal interconnection structure of a semiconductor device, comprising a first metal film pattern disposed on an upper part of an insulation film of a semiconductor substrate; an intermetallic dielectric film having a metal contact plug in which a barrier layer, a metal film for contact plug and a second metal film are sequentially disposed, on the first metal film pattern; and a second metal film pattern disposed on the metal contact plug and intermetallic dielectric film and connected to the metal contact plug.

Abstract: A method for conductive line of semiconductor device is disclosed. A cobalt silicide layer is formed on an impurity junction region exposed through a contact hole. The cobalt silicide layer stabilizes a contact resistance so that the contact resistance of the impurity junction region does not vary in subsequent thermal processes.

Abstract: A method for forming a bit line of a semiconductor device, in which tungsten is deposited just after depositing a metallic barrier layer, a nitride layer is deposited after forming a bit line to prevent the bit line from oxidation due to the exposure of tungsten, and then a rapid thermal treatment is performed, whereby the contact resistance of the bit line is stabilized, and an additional process of depositing TiN due to the micro crack generated by the rapid thermal treatment is not needed, so the manufacturing process becomes simple and the productivity of manufacturing the semiconductor device is improved.

Abstract: A method for forming a bit line of a semiconductor device wherein a first opening in an interlayer insulation film is formed in a P+ S/D (source/drain) region, a post etch treatment (PET) for stabilizing the resistance in the P+ S/D opening is performed, followed by the subsequent formation of a second opening in the N+ S/D region, such that any increase of the resistance of the N+ S/D opening by the PET is thereby prevented.

Abstract: Disclosed is a method for forming a metal contact of a semiconductor device. The method includes the steps of preparing a substrate formed with a tungsten bit line, forming an insulating interlayer on an entire surface of the substrate, forming a contact hole expositing the tungsten bit line, depositing a first tungsten layer on the insulating interlayer through an IMP process, depositing a second tungsten layer on the first tungsten layer through a CMP process, and performing an etch back process with respect to the second tungsten layer. After depositing the first tungsten layer through the IMP process, the second tungsten layer is deposited trough the CVD process without forming the barrier metal. Thus, contact filling failure is prevented when CVD tungsten is deposited, thereby preventing metal contact failure while improving reliability and a yield rate of the semiconductor devices.

Abstract: The disclosure pertains to a method for forming a metal layer of a semiconductor device including the steps of: removing a residual native oxide from a contact hole forming a metal junction layer on this contact hole to improve the junction with an inter-layer insulating film, forming a first metal layer in the contact hole to a predetermined thickness under a low pressure to improve step coverage, and forming a second metal layer to a predetermined thickness, thereby planarizing the metal layer. As a result, the step coverage of the bottom surface and side walls of the contact hole is improved, thus preventing defects caused by the disconnection of metal wire of a semiconductor device and improving the economy of the process.

Abstract: A method for forming a bit line of a semiconductor device wherein a first opening in a P+S/D region, and then forming a second opening in an N+S/D region to prevent increase of the resistance in the N+source/drain (S/D) region opening during a post etch treatment (PET) for stabilizing the resistance in a P+S/D region opening is disclosed.

Abstract: A method of forming contact for a semiconductor device is disclosed.

Abstract: A method for forming a bit line of a semiconductor device, in which tungsten is deposited just after depositing a metallic barrier layer, a nitride layer is deposited after forming a bit line to prevent the bit line from oxidation due to the exposure of tungsten, and then a rapid thermal treatment is performed, whereby the contact resistance of the bit line is stabilized, and an additional process of depositing TiN due to the micro crack generated by the rapid thermal treatment is not needed, so the manufacturing process becomes simple and the productivity of manufacturing the semiconductor device is improved.

Abstract: The disclosure pertains to a method for forming a metal layer of a semiconductor device including the steps of: removing a residual native oxide from a contact hole forming a metal junction layer on this contact hole to improve the junction with an inter-layer insulating film, forming a first metal layer in the contact hole to a predetermined thickness under a low pressure to improve step coverage, and forming a second metal layer to a predetermined thickness, thereby planarizing the metal layer. As a result, the step coverage of the bottom surface and side walls of the contact hole is improved, thus preventing defects caused by the disconnection of metal wire of a semiconductor device and improving the economy of the process.

Abstract: A method for forming metal interconnection of semiconductor device is disclosed. In the present invention, an aluminum layer in the 10 to 100 .ANG. range is deposited on the bottom of the contact before or after the deposition of a titanium layer for barrier metal, which forms TiAl.sub.3 by the reaction of titanium and aluminum. According to the invention, stable contact resistance and low leakage current can be obtained in the application of ultra shallow junction.

Abstract: A method for forming a barrier metal layer of semiconductor device is disclosed. According to the present invention, pre-cleaning, oxygen plasma treatment and formation of barrier metal layer are performed by in-situ type in one same conventional chamber. This method results in the reduction of cost and process time.