Abstract: The present disclosure relates to a BCH encoding, decoding, and multi-stage decoding circuits and method, and an error correction circuit of a flash memory device using the same. The concatenated BCH multi-stage decoding circuit includes: a first stage encoding unit that receives a part or all of data input to a flash memory device, performs BCH encoding, and outputs a first output BCH code or a parity bit thereof; an interleaving unit that receives a part or all of data input to the flash memory device, interleaves, and outputs the data, and a second stage encoding unit that performs BCH encoding of the BCH code or data that is the output of the interleaving unit, and outputs a second output BCH code or a parity bit thereof.

Abstract: A data processing block that includes a syndrome computation unit suitable for generating odd syndrome values in response to a received codeword, an ELP solver suitable for generating even syndrome values, based on the odd syndrome values in a first mode, and generating an error location polynomial, based on the odd syndrome values and the even syndrome values in a second mode, and a Chien search unit suitable for generating solutions of the error location polynomial.

Abstract: Provided is an operating method of a data processing system which includes a data storage device and a host device. The operating method includes reading data at the data storage device based on a request from the host device, and performing an error correction code (ECC) decoding operation on the read data, and performing an additional ECC decoding operation at the host device when the ECC decoding operation performed by the data storage device fails.