Abstract: Disclosed are a thin film solar cell and a method of manufacturing the thin film solar cell. The thin film solar cell according to an exemplary embodiment of the present invention thin film solar cell includes a substrate: a front electrode layer formed on the substrate; an oxide layer formed on the front electrode layer: a light absorbing layer (intrinsic layer) formed on the oxide layer; and a back electrode layer formed on the light absorbing layer, wherein the oxide layer is formed of a material selected from MoO3, WO3, V2O5, NiO and CrO3.

Abstract: Disclosed are a thin film solar cell and a method of manufacturing the thin film solar cell. The thin film solar cell according to an exemplary embodiment of the present invention thin film solar cell includes a substrate: a front electrode layer formed on the substrate; an oxide layer formed on the front electrode layer: a light absorbing layer (intrinsic layer) formed on the oxide layer; and a back electrode layer formed on the light absorbing layer, wherein the oxide layer is formed of a material selected from MoO2, WO2, V2O5, NiO and CrO3.

Abstract: Disclosed is an adsorptive ball for recovering precious metals and resources, a method for manufacturing the adsorptive bale, a flow through-continuous deionization (FT-CDI) module capable of recovering precious metals by using the adsorptive ball, and a flow through-continuous deionization (FT-CDI) apparatus having the flow through-continuous deionization (FT-CDI) installed thereat.

Abstract: The present invention relates to an electrolytic cell for an FT-CDI including: an injection port into which a bead and a concentrate are injected and a discharge port through which the bead and the concentrate are discharged to circulate the bead, thereby preventing the concentration of the bead from being degraded and disposes a mesh at a place in which the concentrate and the bead are received to disperse the concentrate and the bead well.

Abstract: A method of forming a pattern for a semiconductor device includes forming first pattern data, forming second pattern data, forming third pattern data, forming pattern density measurement data including the first, second, and third pattern data, measuring a pattern density of the pattern density measurement data, adjusting shapes of patterns in the third pattern data based on a comparison of the measured density value and a reference density so as to form fourth pattern data, and forming final pattern data including the first, second, and fourth pattern data.

Abstract: A method of adjusting pattern density includes determining a reference pattern density, defining dummy generation fields and designed patterns, forming basic dummy patterns on the dummy generation fields, evaluating a total pattern density from a sum of a density of the designed patterns and a density of the basic dummy patterns, adjusting a size of the basic dummy patterns so that the total pattern density reaches the reference pattern density, and combining data of the adjusted dummy patterns with data of the designed patterns.

Abstract: A highly integrated semiconductor device operates at a high speed due to low resistance at the gate electrode and minimal parasitic capacitance between the gate electrode and substrate. A gate pattern is formed on a substrate, and an insulating layer is formed over the substrate including over the gate pattern. The thickness of the insulating layer is reduced until the upper surface thereof beneath the level of the upper surface of the gate electrode. A conductive layer is then formed on the substrate, and is anisotropically etched to thereby form wings constituting a first spacer on upper sidewalls of the gate pattern. Then, the insulating layer is etched to leave a portion thereof beneath the wings. This remaining portion of the insulating layer constitutes a capacitance preventative layer that serves as a measure against the subsequent forming of a parasitic capacitor when source/drain electrodes are formed by implanting ions into the substrate and heat-treating the same.

Abstract: A highly integrated semiconductor device operates at a high speed due to low resistance at the gate electrode and minimal parasitic capacitance between the gate electrode and substrate. A gate pattern is formed on a substrate, and an insulating layer is formed over the substrate including over the gate pattern. The thickness of the insulating layer is reduced until the upper surface thereof beneath the level of the upper surface of the gate electrode. A conductive layer is then formed on the substrate, and is anisotropically etched to thereby form wings constituting a first spacer on upper sidewalls of the gate pattern. Then, the insulating layer is etched to leave a portion thereof beneath the wings. This remaining portion of the insulating layer constitutes a capacitance preventative layer that serves as a measure against the subsequent forming of a parasitic capacitor when source/drain electrodes are formed by implanting ions into the substrate and heat-treating the same.

Abstract: The present invention provides a method of fabricating trench isolation structures of a semiconductor device. A conformal trench filler insulation layer is formed to fill wide and narrow trenches in a substrate. A portion of the trench filler insulation layer filling the wide trench is then removed. Next, a trench protection layer is formed on the trench filler insulation layer. The resultant structure is planarized to leave the trench protection layer over the wide width trench. Another planarization process is then carried out using the etch mask pattern and the remaining trench protection layer as a planarization stopper. Accordingly, the device isolation layer will attain a uniform planarity irrespective of the various widths of the trenches.

Abstract: A highly integrated semiconductor device operates at a high speed due to low resistance at the gate electrode and minimal parasitic capacitance between the gate electrode and substrate. A gate pattern is formed on a substrate, and an insulating layer is formed over the substrate including over the gate pattern. The thickness of the insulating layer is reduced until the upper surface thereof beneath the level of the upper surface of the gate electrode. A conductive layer is then formed on the substrate, and is anisotropically etched to thereby form wings constituting a first spacer on upper sidewalls of the gate pattern. Then, the insulating layer is etched to leave a portion thereof beneath the wings. This remaining portion of the insulating layer constitutes a capacitance preventative layer that serves as a measure against the subsequent forming of a parasitic capacitor when source/drain electrodes are formed by implanting ions into the substrate and heat-treating the same.

Abstract: The present invention provides a method of fabricating trench isolation structure of a semiconductor device. A conformal trench filler insulation layer is formed to fill wide and narrow trenches in a substrate. A portion of the trench filler insulation layer filling the wide trench is then removed. Next, a trench protection layer is formed on the trench filler insulation layer. The resultant structure is planarized to leave the trench protection layer over the wide width trench. Another planarization process is then carried out using the etch mask pattern and the remaining trench protection layer as a planarization stopper. Accordingly, the device isolation layer will attain a uniform planarity irrespective of the various widths of the trenches.