Abstract: A prosthetic intervertebral disc and methods for using the same are provided. The subject prosthetic discs are characterized by including top and bottom endplates separated by a fibrous compressible element that includes an annular region and a nuclear region. The two plates are held together at least one fiber wound around at least one region of the top endplate and at least one region of the bottom endplate. The subject discs may be employed with separate vertebral body fixation elements, or they may include integrated vertebral body fixation elements. Also provided are kits and systems that include the subject prosthetic discs.

Abstract: A circuit for generating a data strobe signal of a semiconductor memory device comprises a plurality of internal clock delay units, a selecting control unit and a pulse generating unit. The plurality of internal clock delay units delay an internal clock signal in response to a plurality of CAS latency signal. The selecting control unit logically combines a data latch control signal to latch input data with output signals from the plurality of internal clock delay units. The pulse generating unit generates the data strobe signal having a predetermined pulse in response to an output signal from the selecting control unit. In the circuit, a tDQSS margin is regulated depending on change of tCK of an operating frequency in response to a CAS latency signal.

Abstract: A liquid crystal display system reduces a consumed current and reduces generation of heat in a data integrated circuit. The liquid crystal display device includes a liquid crystal cell array, a first charge sharing circuit arranged on one side of the liquid crystal cell array to pre-charge the data lines before the data lines are charged with a data voltage, and a second charge sharing circuit arranged outside the other side of the liquid crystal cell array to pre-charge the data lines before the data lines are charged with a data voltage.

Abstract: A liquid crystal display device includes a first transistor that outputs a charge share voltage to a data line in response to a first output control signal. A second transistor outputs a pre-charge voltage, which is greater than the charge share voltage, to the data line in response to a second output control signal which is delayed in phase from the first output control signal. A third transistor outputs a data voltage to the data line in response to at least one of the first and second output control signals. A logic circuit controls the transistors in response to the output control signals and a polarity control signal that controls the polarity of the data voltage.

Abstract: A liquid crystal display device is set forth that comprises a data line that is connected to drive a liquid crystal cell and an output driver connected to selectively provide a pixel drive signal to the data line. The pixel drive signal corresponds to a digital video data signal provided to the liquid crystal display device. A pre-charging circuit is used to reduce the power consumed by the output driver. To this end, the pre-charging circuit is connected to selectively pre-charge the data line to one or more of a plurality of voltage levels depending on the value of the digital video data signal. In one embodiment, the plurality of voltage levels comprises a positive pre-charge voltage, a negative pre-charge voltage, and a charge share voltage. The magnitudes of the positive pre-charge voltage and the negative pre-charge voltage may be chosen so that they are greater than the magnitude of the charge share voltage.

Abstract: A liquid crystal display device includes a comparator which judges a voltage of data; and a pre-charge controller which pre-charges a data line of a liquid crystal display panel with a pre-charge voltage if the voltage of the data is a first voltage, and pre-charges the data line with a charge share voltage, which has a lower absolute value than the pre-charge voltage, if the voltage of the data is a second voltage that is lower than the first voltage.

Abstract: A circuit for generating a data strobe signal of a semiconductor memory device comprises a plurality of internal clock delay units, a selecting control unit and a pulse generating unit. The plurality of internal clock delay units delay an internal clock signal in response to a plurality of CAS latency signal. The selecting control unit logically combines a data latch control signal to latch input data with output signals from the plurality of internal clock delay units. The pulse generating unit generates the data strobe signal having a predetermined pulse in response to an output signal from the selecting control unit. In the circuit, a tDQSS margin is regulated depending on change of tCK of an operating frequency in response to a CAS latency signal.

Abstract: Disclosed is a method of controlling an MRS operation in a memory device which can prevent an unnecessary MRS operation due to a malfunction of the memory device at a time when the memory device exits from a self-refresh mode. According to this method, external addresses are used to intercept a mode register set command signal that enables the MRS operation at a time point at which the memory device exits from the self-refresh mode.

Abstract: A local input/output line precharge circuit of a semiconductor memory device comprises a precharge control unit, an equalization unit and a data output unit. The precharge control unit outputs a precharge control signal to precharge a pair of local input/output lines in response to a continuous write signal activated when a write operation continues. The equalization unit precharges and equalizing the pair of local input/output lines in response to the precharge control signal. The data output unit outputs data signals of a pair of global input/output lines to the pair of local input/output lines in response to output signal from the equalization unit. In the circuit, a local input/output line precharge operation is not performed at a continuous write mode, thereby reducing current consumption.

Abstract: A motor includes a stator including a rim portion and a central portion, with the rim portion including through holes and the center portion including a through opening. A rotor installed in the through opening of the stator includes at least one rotational shaft extending from a rotating center of the rotor, such that the rotor rotating as a result of electrical interaction between the stator and the rotor. A first bracket of the motor includes fastening bars that pass through the through holes of the stator, and include elastically deformable elastic fingers. A second bracket of the motor includes fastening holes formed in positions corresponding to the fastening bars of the first bracket and engaging the elastic fingers of the fastening bars.

Abstract: A prosthetic intervertebral disc and methods for using the same are provided. The subject prosthetic discs are characterized by including top and bottom endplates separated by a fibrous compressible element that includes an annular region and a nuclear region. The two plates are held together at least one fiber wound around at least one region of the top endplate and at least one region of the bottom endplate. The subject discs may be employed with separate vertebral body fixation elements, or they may include integrated vertebral body fixation elements. Also provided are kits and systems that include the subject prosthetic discs.