Patents by Inventor Sung-han Choi
Sung-han Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127710Abstract: Disclosed are a system and method for automatically evaluating an essay. The system includes a structure analysis module configured to divide learning data and learner essay text in a predetermined structure analysis unit, generate structure tagging information for each structure analysis unit, and structure the learning data and the learner essay text by attaching the structure tagging information to the learning data and the learner essay text, a learning module configured to generate an essay evaluation model through learning by using essay text that is included in the structured learning data and the structure tagging information as an input value and using an evaluation score that is included in the structured learning data as a label, and an evaluation module configured to generate essay evaluation results using the essay evaluation model.Type: ApplicationFiled: April 18, 2023Publication date: April 18, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Minsoo CHO, Oh Woog KWON, Yoon-Hyung ROH, Ki Young LEE, Yo Han LEE, Sung Kwon CHOI, Jinxia HUANG
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Publication number: 20240114807Abstract: An integrated circuit includes a field effect transistor (FET) and a phase change memory (PCM) cell. The PCM cell includes a heater, wherein a bottom surface of the heater is at or below a top surface of the FET.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Inventors: Victor W.C. Chan, JIN PING HAN, Samuel Sung Shik Choi, Injo Ok
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Patent number: 11890604Abstract: Provided is a carbon dioxide reduction composite catalyst, comprising an organic-inorganic porous body, and a molecular reduction catalyst combined with the organic-inorganic porous body, wherein the organic-inorganic porous body includes metal oxide clusters, and a light-condensing organic material as linkers between the metal oxide clusters, and the linkers absorb visible light to form excitons, and move the excitons through energy transfer between the linkers to transfer the electrons of the excitons to the molecular reduction catalyst.Type: GrantFiled: February 25, 2021Date of Patent: February 6, 2024Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, SEJONG CAMPUSInventors: Ho Jin Son, Sang Ook Kang, Sung Han Choi, Chul Hoon Kim
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Publication number: 20210220809Abstract: Provided is a carbon dioxide reduction composite catalyst, comprising an organic-inorganic porous body, and a molecular reduction catalyst combined with the organic-inorganic porous body, wherein the organic-inorganic porous body includes metal oxide clusters, and a light-condensing organic material as linkers between the metal oxide clusters, and the linkers absorb visible light to form excitons, and move the excitons through energy transfer between the linkers to transfer the electrons of the excitons to the molecular reduction catalyst.Type: ApplicationFiled: February 25, 2021Publication date: July 22, 2021Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, SEJONG CAMPUSInventors: Ho Jin SON, Sang Ook KANG, Sung Han CHOI, Chul Hoon KIM
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Patent number: 7450667Abstract: An apparatus decodes data of unknown frame length. The decoding apparatus includes a preliminary decoding part and a decoded data outputting part. The preliminary decoding part decodes data into preliminarily decoded data according to each of the possible frame lengths. The decoded data outputting part selectively outputs data among the preliminary decoding data that correspond to a detected frame length. Accordingly, memory can be efficiently utilized, and decoding efficiency deterioration is prevented.Type: GrantFiled: July 3, 2001Date of Patent: November 11, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hong Kim, Jun-Jin Kong, Sung-Han Choi
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Patent number: 6820232Abstract: A device for detecting in a receiver whether any transmission errors have occurred in the received CRC code, in a case that a transmitter transmits the CRC code created by sequencing the parity bits, which are generated using the generator polynomial, in the reverse order and appending them to the message bits. The device comprises a division unit for dividing the message bits by the parity bit generator polynomial to form the remainder, a comparison unit for bitwise comparing the remainder bits with the reverse ordered parity bits, and a decision unit for deciding whether transmission errors have occurred in the CRC code based on the results of the comparison unit. According to the present invention, the transmission errors in the received CRC code are effectively detected, when the CRC code includes the parity bits sequenced in the reverse order, unlike the conventional normal order.Type: GrantFiled: July 17, 2001Date of Patent: November 16, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-hong Kim, Jun-jin Kong, Sung-han Choi
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Patent number: 6799296Abstract: A high speed Viterbi detector for an optical disk system, includes a frequency dividing unit for generating an auxiliary clock at one-third of the main clock frequency, a branch metric calculation unit for calculating each of a plurality of branch metrics, a serial-to-parallel converting unit for outputting each of the branch metrics at the main clock frequency in units of 3 state bits, an addition/comparison/selection unit for adding the branch metrics and previously stored state metrics and for comparing the addition results to select and output the minimum of the addition results as a new state metric, and for outputting a corresponding path selection signal, at the auxiliary clock frequency, a path memory for storing the path selection signal and for outputting parallel data corresponding to the path selection signal, at the auxiliary clock frequency, and a parallel-to-serial converting unit for converting the path memory output into serial data.Type: GrantFiled: November 1, 2001Date of Patent: September 28, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-jin Kong, Sung-han Choi, Jae-wook Lee
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Publication number: 20020083392Abstract: A device for detecting in a receiver whether any transmission errors have occurred in the received CRC code, in a case that a transmitter transmits the CRC code created by sequencing the parity bits, which are generated using the generator polynomial, in the reverse order and appending them to the message bits. The device comprises a division unit for dividing the message bits by the parity bit generator polynomial to form the remainder, a comparison unit for bitwise comparing the remainder bits with the reverse ordered parity bits, and a decision unit for deciding whether transmission errors have occurred in the CRC code based on the results of the comparison unit. According to the present invention, the transmission errors in the received CRC code are effectively detected, when the CRC code includes the parity bits sequenced in the reverse order, unlike the conventional normal order.Type: ApplicationFiled: July 17, 2001Publication date: June 27, 2002Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Hong Kim, Jun-Jin Kong, Sung-Han Choi
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Publication number: 20020057747Abstract: An apparatus decodes data of unknown frame length. The decoding apparatus includes a preliminary decoding part and a decoded data outputting part. The preliminary decoding part decodes data into preliminarily decoded data according to each of the possible frame lengths. The decoded data outputting part selectively outputs data among the preliminary decoding data that correspond to a detected frame length. Accordingly, memory can be efficiently utilized, and decoding efficiency deterioration is prevented.Type: ApplicationFiled: July 3, 2001Publication date: May 16, 2002Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Hong Kim, Jun-Jin Kong, Sung-Han Choi
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Publication number: 20020053061Abstract: A high speed Viterbi detector for an optical disk system, includes a frequency dividing unit for generating an auxiliary clock at one-third of the main clock frequency, a branch metric calculation unit for calculating each of a plurality of branch metrics, a serial-to-parallel converting unit for outputting each of the branch metrics at the main clock frequency in units of 3 state bits, an addition/comparison/selection unit for adding the branch metrics and previously stored state metrics and for comparing the addition results to select and output the minimum of the addition results as a new state metric, and for outputting a corresponding path selection signal, at the auxiliary clock frequency, a path memory for storing the path selection signal and for outputting parallel data corresponding to the path selection signal, at the auxiliary clock frequency, and a parallel-to-serial converting unit for converting the path memory output into serial data.Type: ApplicationFiled: November 1, 2001Publication date: May 2, 2002Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-Jin Kong, Sung-han Choi, Jae-wook Lee
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Patent number: 6317472Abstract: An apparatus for providing and storing a state metric which is used for an add-compare-select (ACS) operation in a Viterbi decoder using a number of ACS units in order to enhance decoding speed. A state metric memory in Viterbi decoder uses a two-port memory, in which a memory bank for reading and writing a state metric of a first half among the N state metrics generated in a ACS unit and two memory banks for alternately reading and writing the state metric of the second half whenever a codeword is input, are incorporated into a single memory. As a result, the storage capacity for storing the state metrics can be greatly reduced as compared to a conventional apparatus.Type: GrantFiled: August 6, 1998Date of Patent: November 13, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-han Choi, Jun-jin Kong