Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.

Abstract: A quantum dot including a core that includes a first semiconductor nanocrystal including zinc and selenium, and optionally sulfur and/or tellurium, and a shell that includes a second semiconductor nanocrystal including zinc, and at least one of sulfur or selenium is disclosed. The quantum dot has an average particle diameter of greater than or equal to about 13 nm, an emission peak wavelength in a range of about 440 nm to about 470 nm, and a full width at half maximum (FWHM) of an emission wavelength of less than about 25 nm. A method for preparing the quantum dot, a quantum dot-polymer composite including the quantum dot, and an electronic device including the quantum dot is also disclosed.

Abstract: Provided is a method for purifying an anti-4-1BB/anti-HER2 bispecific antibody, the method of which includes carrying out affinity chromatography with a sodium acetate buffer containing a certain inorganic salt as an elution buffer. The purification method of the presently claimed subject matter increases the elution of an antibody in the intact form, thereby being able to provide an anti-4-1BB/anti-HER2 bispecific antibody in the intact form in high purity and high yield.

Abstract: A power module for a vehicle, includes: a first substrate including a first metal circuit disposed on a 1-1st surface, and a first spacer extending from the first metal circuit in a first direction; a second substrate spaced from and facing the first substrate in a second direction, and including a second metal circuit disposed on a 2-1st surface facing the 1-1st surface, and a second spacer extending from the second metal circuit in the second direction; and a semiconductor chip disposed between the first substrate and the second substrate and including a power pad and a signal pad, the first spacer and the second spacer extending toward each other, and the second spacer including a 2-1st spacer connected to the power pad and a 2-2nd spacer connected to the signal pad.

Abstract: A display device may include pixels on a substrate. Each of the pixels may include: a first alignment electrode and a second alignment electrode located on the substrate and spaced from each other; a first insulating layer on the first alignment electrode and the second alignment electrode; a light emitting element located on the first insulating layer between the first and second alignment electrodes; a dummy pattern located between the first insulating layer and the light emitting element; a second insulating layer located on the light emitting element and exposing first and second ends of the light emitting element; a first electrode electrically connected to the first end of the light emitting element; and a second electrode spaced from the first electrode, and electrically connected to the second end of the light emitting element. The dummy pattern may include a same material as the second insulating layer.

Abstract: The present invention relates to a heteroaryl derivative compound and a use thereof. Since the heteroaryl derivative of the present invention exhibits excellent inhibitory activity against EGFR, the heteroaryl derivative can be usefully used as a therapeutic agent for EGFR-associated diseases.

Abstract: A display device includes: light emitting elements, each of the light emitting elements including a first end having a first polarity and a second end having a second polarity different from the first polarity; and a first type connection electrode contacting the first ends and/or the second ends of the light emitting elements, wherein a first type connection electrode includes: a middle portion extending in a first direction; a first electrode portion extending from the middle portion toward a first side in a second direction intersecting the first direction; a second electrode portion extending from the middle portion toward the first side in the second direction and spaced from the first electrode portion by a first width in the first direction; a third electrode portion extending from the middle portion toward a second side in the second direction; and a fourth electrode portion.

Abstract: The present invention relates to an apparatus and method for encoding and decoding an image by skip encoding. The image-encoding method by skip encoding, which performs intra-prediction, comprises: performing a filtering operation on the signal which is reconstructed prior to an encoding object signal in an encoding object image; using the filtered reconstructed signal to generate a prediction signal for the encoding object signal; setting the generated prediction signal as a reconstruction signal for the encoding object signal; and not encoding the residual signal which can be generated on the basis of the difference between the encoding object signal and the prediction signal, thereby performing skip encoding on the encoding object signal.

Abstract: The present invention relates to a conjugate comprising oxyntomodulin, an immunoglobulin Fc region, and non-peptidyl polymer wherein the conjugate being obtainable by covalently linking oxyntomodulin to immunoglobulin Fc region via non-peptidyl polymer, and a pharmaceutical composition for the prevention or treatment of obesity comprising the conjugates. The conjugate comprising oxyntomodulin and the immunoglobulin Fc of the present invention reduces food intake, suppresses gastric emptying, and facilitates lipolysis without side-effects, unlike native oxyntomodulin, and also shows excellent receptor-activating effects and long-term sustainability, compared to native oxyntomodulin. Thus, it can be widely used in the treatment of obesity with safety and efficacy.

Abstract: Embodiments of the present disclosure relate to a neural engine of a neural processor circuit having multiple multiply-add circuits and an accumulator circuit coupled to the multiply-add circuits. The multiply-add circuits perform multiply-add operations of a three dimensional convolution on a work unit of input data using a kernel to generate at least a portion of output data in a processing cycle. The accumulator circuit includes multiple batches of accumulators. Each batch of accumulators receives and stores, after the processing cycle, the portion of the output data for each output depth plane of multiple output depth planes. A corresponding batch of accumulators stores, after the processing cycle, the portion of the output data for a subset of the output channels and for each output depth plane.

Abstract: Embodiments relate to a compiler. The compiler decreases data fetch and read associated with storing data in a data buffer of a neural processor circuit to or from a system memory. The data buffer can store an input slice of data for processing by a neural engine(s) of the neural processor circuit, an output slice of data output from the neural engine(s), and/or an intermediate data slice of data.

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

Abstract: Disclosed are a novel strain of Bacillus amyloliquefaciens, a method of producing fermented grains using the strain, fermented grains produced using the strain, and a composition for thrombolysis; digestion improvement; prophylaxis, amelioration or treatment of bowel inflammation, serous membrane weakening or intestinal injury; or antioxidation, comprising the fermented grains.

Abstract: Embodiments of the present disclosure relate to a neural engine of a neural processor circuit having multiple multiply-add circuits and an accumulator circuit coupled to the multiply-add circuits. The multiply-add circuits perform multiply-add operations of a three dimensional convolution on a work unit of input data using a kernel to generate at least a portion of output data in a processing cycle. The accumulator circuit includes multiple batches of accumulators. Each batch of accumulators receives and stores, after the processing cycle, the portion of the output data for each output depth plane of multiple output depth planes. A corresponding batch of accumulators stores, after the processing cycle, the portion of the output data for a subset of the output channels and for each output depth plane.

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

Abstract: Embodiments relate to a neural processor circuit including a plurality of neural engine circuits, a data buffer, and a kernel fetcher circuit. At least one of the neural engine circuits is configured to receive matrix elements of a matrix as at least the portion of the input data from the data buffer over multiple processing cycles. The at least one neural engine circuit further receives vector elements of a vector from the kernel fetcher circuit, wherein each of the vector elements is extracted as a corresponding kernel to the at least one neural engine circuit in each of the processing cycles. The at least one neural engine circuit performs multiplication between the matrix and the vector as a convolution operation to produce at least one output channel of the output data.

Abstract: Embodiments of the present disclosure relate to a neural engine of a neural processor circuit having multiple multiply-add circuits and an accumulator circuit coupled to the multiply-add circuits. The multiply-add circuits perform multiply-add operations of a three dimensional convolution on a work unit of input data using a kernel to generate at least a portion of output data in a processing cycle. The accumulator circuit includes multiple batches of accumulators. Each batch of accumulators receives and stores, after the processing cycle, the portion of the output data for each output depth plane of multiple output depth planes. A corresponding batch of accumulators stores, after the processing cycle, the portion of the output data for a subset of the output channels and for each output depth plane.

Abstract: Embodiments relate to a compiler. The compiler decreases data fetch and read associated with storing data in a data buffer of a neural processor circuit to or from a system memory. The data buffer can store an input slice of data for processing by a neural engine(s) of the neural processor circuit, an output slice of data output from the neural engine(s), and/or an intermediate data slice of data.

Abstract: Embodiments relate to a neural engine circuit of a neural network processor circuit that performs a convolution operation on input data in a first mode and a parallel sorting operation on input data in a second mode. The neural engine circuit includes a plurality of operation circuits and an accumulator circuit coupled to the plurality of operation circuits. The plurality of operation circuits receives input data. In the first mode, the plurality of operation circuits performs multiply-add operations of a convolution on the input data using a kernel. In the second mode, the plurality of operation circuits performs a portion of a parallel sorting operation on the input data. In the first mode, the accumulator circuit receives and stores first results of the multiply-add operations. In the second mode, the accumulator circuit receives and stores second results of the parallel sorting operation.

Abstract: Embodiments relate to a compiler. The compiler decreases data fetch and read associated with storing data in a data buffer of a neural processor circuit to or from a system memory. The data buffer can store an input slice of data for processing by a neural engine(s) of the neural processor circuit, an output slice of data output from the neural engine(s), and/or an intermediate data slice of data.