Abstract: A DDR SDRAM operates at a double data rate by accessing the bursts of data having a burst length in accordance with the rising and falling edges of each pulse of a DQS signal. A ringing may occur in the DQS signal causing write failures. To mask the ringing, a DQS buffer generates a first access signal at the rising edge of each DQS pulse generated in presence of the data burst. The DQS buffer also generates a second access signal at the falling edge of each DQS pulse. Each of the first and second access signals includes a finite number of pulses based on the total number of rising and falling edges of the DQS signal. Two consecutive data bursts are accessed together for a write operation for each pair of the consecutive first and second access signals. After accessing all data bursts, a mask time is calculated to disable the DQS buffer, by which the ringing is masked.

Abstract: A method for controlling speakers in a mobile station comprises detecting a movement of the mobile station. The method also comprises differentially controlling sound output by the speakers based on the detected movement of the mobile station. The differentially controlling the sound output by the speakers based on the detected movement of the mobile station may comprise at least one of adjusting a sound volume and selecting a sound effect. The detecting the movement of the mobile station may comprise detecting a tilt of the mobile station.

Abstract: A DDR SDRAM operates at a double data rate by accessing the bursts of data having a burst length in accordance with the rising and falling edges of each pulse of a DQS signal. A ringing may occur in the DQS signal causing write failures. To mask the ringing, a DQS buffer generates a first access signal at the rising edge of each DQS pulse generated in presence of the data burst. The DQS buffer also generates a second access signal at the falling edge of each DQS pulse. Each of the first and second access signals includes a finite number of pulses based on the total number of rising and falling edges of the DQS signal. Two consecutive data bursts are accessed together for a write operation for each pair of the consecutive first and second access signals. After accessing all data bursts, a mask time is calculated to disable the DQS buffer, by which the ringing is masked.

Abstract: A semiconductor memory device includes a first data scramble circuit, which is configured between a data input buffer and a memory cell block, for outputting data by inverting or maintaining a polarity of an input data in response to a data scramble control signal and a second data scramble circuit, which is configured between the memory cell block and a data output buffer, for outputting data by inverting or maintaining a polarity of an output data in response to a data scramble control signal.

Abstract: Disclosed is a semiconductor memory device capable of improving a timing margin in a logic circuit using a signal latch. The semiconductor memory device according to the present invention includes an address generator including a latch circuit, wherein the address generator receives an external address signal from an external circuit and latches the external address signal in response to a control signal; and a Y-predecoder for receiving outputs from the address generator and for generating a pulse in response to the control signal. Accordingly, the semiconductor memory device according to the present invention transfers a signal at safety without considering a separate timing margin, by using the control signal in an adjacent circuit as an enable signal.