Abstract: A method, codec device, and system on chip (SoC) are provided for coding a region of interest (ROI) object of a frame. A current frame, which includes the ROI object is received, and a type of the current frame is determined. A complexity of the current frame is estimated. An ROI control signal is generated for controlling ROI coding of the ROI object based on the complexity.

Abstract: A video encoding device is provided. The video encoding device includes a first encoder including a prediction module, which performs an intra prediction operation or an inter prediction operation on a plurality of first blocks included in a first frame, and a second encoder encoding a second frame, which is different from the first frame, and not including the prediction module, wherein if the inter prediction operation is performed on the first blocks, the prediction module transmits first information regarding a motion estimation operation to the second encoder, and the second encoder includes a prediction block generation module, which receives the first information and generates a prediction block by performing a motion compensation operation on a plurality of second blocks included in the second frame based on the first information.

Abstract: A video encoding apparatus may include a memory storing interest region information for each of a plurality of scenarios and a neural processing unit (NPU) extracting interest region information corresponding to a scenario of an input video from the memory or updating the interest region information stored in the memory based on an user input.

Abstract: A video encoding apparatus may include a partitioning unit which divides a frame included in input video into a plurality of blocks and a rate control module which adjusts a first quantization parameter value of a block corresponding to a region of interest among the plurality of blocks based on a first CBF (current buffer fullness) value of the region of interest, and adjusts a second quantization parameter value of a block corresponding to a non-region of interest among the plurality of blocks based on a second CBF value of the non-region of interest.

Abstract: A video processing device configured to encode frames divided into a plurality of layers according to a prediction type includes a pre-processing circuit configured to, generate a mode analysis result by analyzing mode information for each of N neighboring frames neighboring a target frame, and determine a target layer bit numbers allocated to each of the plurality of layers based on the mode analysis result, N being an integer equal to or greater than 2; and a first encoder configured to encode the target frame according to the determined target layer bit numbers.

Abstract: A codec according to an exemplary embodiment includes a codec processor which receives a current frame, determines a type of a received current frame, and sets rate control parameters of the current frame, and a bit-rate estimator which allocates total target bits to a first group of picture (GOP) including the current frame, and allocates a target bit to each of frames included in the first GOP based on a determined type of the current frame and set rate control parameters.

Abstract: In a method of encoding video data, an input picture is divided into a first picture corresponding to a region of interest (ROI) and a second picture corresponding to a non-region of interest (non-ROI). A third picture is generated by down-scaling the second picture. A quantization parameter for the ROI is determined based on the first picture. A quantization parameter for the non-ROI is determined based on the third picture. A compressed picture is generated by encoding the input picture based on the quantization parameter for the ROI and the quantization parameter for the non-ROI.

Abstract: An encoder comprises a rate controller and a quantizer. The rate controller may be configured to compare an activity of a current block with an average activity of a previous frame; determine a quantization parameter offset according to the comparison between the activity of the current block and the average activity of the previous frame. Lastly, the rate controller may be configured to determine a quantization parameter using the quantization parameter offset. The quantizer in the encoder may be configured to quantize the current block using the quantization parameter.

Abstract: A codec according to an exemplary embodiment includes a codec processor which receives a current frame, determines a type of a received current frame, and sets rate control parameters of the current frame, and a bit-rate estimator which allocates total target bits to a first group of picture (GOP) including the current frame, and allocates a target bit to each of frames included in the first GOP based on a determined type of the current frame and set rate control parameters.

Abstract: A method, codec device, and system on chip (SoC) are provided for coding a region of interest (ROI) object of a frame. A current frame, which includes the ROI object is received, and a type of the current frame is determined. A complexity of the current frame is estimated. An ROI control signal is generated for controlling ROI coding of the ROI object based on the complexity.

Abstract: A CMOS image sensor and a method for fabricating the same are disclosed. The method includes forming a plurality of color filters on a substrate, each color filter having a curvature, and forming microlenses on the color filters that each has a radius of curvature that varies with the wavelength of the color filter on which it is formed.

Abstract: A pattern mask for forming a microlens includes mask pattern parts alternately arranged and corresponding to pixel regions in a matrix, wherein neighboring corners of the mask pattern parts overlap with each other.

Abstract: An image sensor may include a dielectric, a metal interconnection, an align key, a first substrate, a photodiode, and a transparent electrode. The first substrate may include a pixel region, a peripheral circuitry region and a scribe lane. The dielectric may include a metal interconnection and an align key over the first substrate. The photodiode may be formed over the pixel region and the scribe lane. The transparent electrode may be formed over the photodiode. The align key may have a protrusion formed in a center thereof.

Abstract: An image sensor includes a lower metal interconnection, an interlayer dielectric, a first substrate, a photodiode, an upper electrode and an amorphous silicon layer. The lower metal interconnection and the interlayer dielectric are formed over the first substrate including a pixel region and a peripheral region. The photodiode is formed over the pixel region of the first substrate. The upper electrode layer is connected to the photodiode. The amorphous silicon layer is formed between the photodiode and the interlayer dielectric.

Abstract: Embodiments relate to an image sensor and a method for manufacturing the same. According to embodiments, a semiconductor substrate may include a pixel part and a peripheral part. A photo diode pattern may be formed over the pixel part having a height that is greater than a height of a surface of an interlayer dielectric film over the peripheral part. A device isolation film and a metal layer may be provided over the photodiode and over interlayer dielectric film over the peripheral part. A planarization layer may be provided and may compensate for a height difference so that a first metal film pattern connected to the photo diode pattern and a second metal film pattern connected to the metal wire in peripheral part may be simultaneously formed by patterning the planarization layer and metal film.

Abstract: A method for manufacturing a semiconductor device including coating a photo-resist layer on a semiconductor substrate having a lower layer; performing a soft-bake process on the photo-resist layer; performing an exposure process on the photo-resist layer having passed through the soft-bake process; performing a post exposure-bake (PEB) process on photo-resist pattern holes formed by the exposure process; performing a developing process on the photo-resist pattern holes having passed through the PEB process; and performing a hard-bake process on the photo-resist pattern holes having passed through the developing process. The method improves the circularity of PR pattern holes to improve the profile of contacts in an etching process after a photography process, resulting in an enhancement in the operation reliability of the device.

Abstract: An image sensor may include a readout circuit formed over a first substrate made of InSb, the first substrate including a pixel part and a periphery part. A wiring and interlayer dielectric layer may be formed over the first substrate including the readout circuit. A photodiode may be formed over the interlayer dielectric layer and over the pixel part of the first substrate, and an upper electrode layer may be connected with the photodiode.

Abstract: A CMOS image sensor and a method for fabricating the same are disclosed. The method includes forming a plurality of color filters on a substrate, each color filter having a curvature, and forming microlenses on the color filters that each has a radius of curvature that varies with the wavelength of the color filter on which it is formed.

Abstract: An image sensor includes a lower metal interconnection, an interlayer dielectric, a first substrate, a photodiode, an upper electrode and an amorphous silicon layer. The lower metal interconnection and the interlayer dielectric are formed over the first substrate including a pixel region and a peripheral region. The photodiode is formed over the pixel region of the first substrate. The upper electrode layer is connected to the photodiode. The amorphous silicon layer is formed between the photodiode and the interlayer dielectric.

Abstract: Embodiments relate to an image sensor and a method for manufacturing the same. According to embodiments, a semiconductor substrate may include a pixel part and a peripheral part. A photo diode pattern may be formed over the pixel part having a height that is greater than a height of a surface of an interlayer dielectric film over the peripheral part. A device isolation film and a metal layer may be provided over the photodiode and over interlayer dielectric film over the peripheral part. A planarization layer may be provided and may compensate for a height difference so that a first metal film pattern connected to the photo diode pattern and a second metal film pattern connected to the metal wire in peripheral part may be simultaneously formed by patterning the planarization layer and metal film.