Abstract: A semiconductor package is provided. The semiconductor package includes a connection structure, a semiconductor chip, and a connection metal. The connection structure includes a redistribution layer and a connection via layer. The semiconductor chip is disposed on the connection structure, and includes a connection pad. The connection metal is disposed on the connection structure and is electrically connected to the connection pad by the connection structure. The connection via layer includes a connection via having a major axis and a minor axis, and in a plan view, the minor axis of the connection via intersects with the connection metal.

Abstract: A semiconductor package includes: a semiconductor chip including a body having a first surface and a second surface, opposing the first surface, a connection pad disposed on the first surface of the body, and an extension pad disposed on the connection pad; and a connection structure including an insulating layer disposed on the first surface of the body of the semiconductor chip, a redistribution via penetrating through the insulating layer and having one side thereof in contact with the extension pad, and a redistribution layer disposed on the insulating layer and having a via pad in contact with the other side of the redistribution via, wherein a horizontal cross-sectional area of extension pad of the semiconductor chip is greater than a horizontal cross-sectional area of the connection pad of the semiconductor chip.

Abstract: A semiconductor package is provided. The semiconductor package includes a connection structure, a semiconductor chip, and a connection metal. The connection structure includes a redistribution layer and a connection via layer. The semiconductor chip is disposed on the connection structure, and includes a connection pad. The connection metal is disposed on the connection structure and is electrically connected to the connection pad by the connection structure. The connection via layer includes a connection via having a major axis and a minor axis, and in a plan view, the minor axis of the connection via intersects with the connection metal.

Abstract: A semiconductor package includes: a semiconductor chip including a body having a first surface and a second surface, opposing the first surface, a connection pad disposed on the first surface of the body, and an extension pad disposed on the connection pad; and a connection structure including an insulating layer disposed on the first surface of the body of the semiconductor chip, a redistribution via penetrating through the insulating layer and having one side thereof in contact with the extension pad, and a redistribution layer disposed on the insulating layer and having a via pad in contact with the other side of the redistribution via, wherein a horizontal cross-sectional area of extension pad of the semiconductor chip is greater than a horizontal cross-sectional area of the connection pad of the semiconductor chip.

Abstract: A fan-out semiconductor package includes: a frame, including a wiring layer, and having a through-hole; a semiconductor chip disposed in the through-hole, and including a connection pad; an encapsulant covering at least a portion of each of the frame and an inactive surface of the semiconductor chip, and having a first opening exposing at least a portion of the wiring layer; an insulating layer disposed on the encapsulant, and having a second opening formed in the first opening to expose at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening; and a connection structure disposed on the frame and an active surface of the semiconductor chip, and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad.

Abstract: A fan-out semiconductor package includes: a frame, including a wiring layer, and having a through-hole; a semiconductor chip disposed in the through-hole, and including a connection pad; an encapsulant covering at least a portion of each of the frame and an inactive surface of the semiconductor chip, and having a first opening exposing at least a portion of the wiring layer; an insulating layer disposed on the encapsulant, and having a second opening formed in the first opening to expose at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening; and a connection structure disposed on the frame and an active surface of the semiconductor chip, and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad.

Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.

Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.

Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.

Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.

Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.

Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.

Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.

Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.

Abstract: A method of manufacturing a semiconductor device having a shallow trench isolation includes steps of forming a mask layer on a semiconductor substrate, forming a shallow trench in a semiconductor substrate using the mask layer, forming at least one step in the semiconductor substrate at the top of the shallow trench, and then forming a liner layer over the entire surface of the semiconductor substrate so as to line the shallow trench and thereby offer protection during subsequent oxidation. When the mask layer is subsequently removed, the at least one step in the semiconductor substrate allows portions of the liner layer extending outside the shallow trench to be removed without creating problematic dents in the structure.

Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.

Abstract: Methods of fabricating a semiconductor device having low-voltage MOS transistors and high-voltage metal-oxide semiconductor (“MOS”) transistors are provided. The method includes forming a device isolation layer at a predetermined region of a semiconductor substrate. The device isolation layer defines first and second active regions in low and high-voltage MOS transistor regions, respectively. A capping layer pattern is formed to cover the low-voltage MOS transistor region. The capping layer pattern exposes the second active region in the high-voltage MOS transistor region. A first gate oxide layer is formed on an entire surface of the semiconductor substrate having the capping layer pattern. The first gate oxide layer is formed using a chemical vapor deposition (“CVD”) technique. The first gate oxide layer serves as a gate insulating layer of the high-voltage MOS transistor.

Abstract: A method of forming a shallow trench isolation of a semiconductor device, includes providing a semiconductor substrate including field and active regions; forming a first insulating layer and a mask layer on the active region that expose the field region; etching the exposed field region to form a shallow trench; etching a portion of the mask layer to recess the mask layer a predetermined distance from an edge of the trench; forming a second insulating layer in the trench, the second insulating layer having a step higher than the active region; forming a liner layer as covering the mask layer and the second insulating layer; forming a third insulating layer as covering the liner layer and filling the trench; etching the mask, liner and third insulating layers to provide a planarized surface; removing the remaining mask layer; and removing the remaining first insulating layer.

Abstract: Methods of fabricating a semiconductor device having low-voltage MOS transistors and high-voltage metal-oxide semiconductor (“MOS”) transistors are provided. The method includes forming a device isolation layer at a predetermined region of a semiconductor substrate. The device isolation layer defines first and second active regions in low and high-voltage MOS transistor regions, respectively. A capping layer pattern is formed to cover the low-voltage MOS transistor region. The capping layer pattern exposes the second active region in the high-voltage MOS transistor region. A first gate oxide layer is formed on an entire surface of the semiconductor substrate having the capping layer pattern. The first gate oxide layer is formed using a chemical vapor deposition (“CVD”) technique. The first gate oxide layer serves as a gate insulating layer of the high-voltage MOS transistor.

Abstract: A method of forming a shallow trench isolation of a semiconductor device, includes providing a semiconductor substrate including field and active regions; forming a first insulating layer and a mask layer on the active region that expose the field region; etching the exposed field region to form a shallow trench; etching a portion of the mask layer to recess the mask layer a predetermined distance from an edge of the trench; forming a second insulating layer in the trench, the second insulating layer having a step higher than the active region; forming a liner layer as covering the mask layer and the second insulating layer; forming a third insulating layer as covering the liner layer and filling the trench; etching the mask, liner and third insulating layers to provide a planarized surface; removing the remaining mask layer; and removing the remaining first insulating layer.