Abstract: An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.

Abstract: An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.

Abstract: A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor connected to the first memory cell transistor, a first dummy word line connected to a gate of the first dummy cell transistor, a first selection transistor connected to the first dummy cell transistor, a first selection line connected to a gate of the first selection transistor, and a voltage control unit connected to the first selection line, the voltage control unit being adapted to output to the first selection line a voltage lower than a voltage applied to the bulk region, in an erasing mode for erasing the first through nth memory cell transistors.

Abstract: High-voltage MOS transistors with a floated drain-side auxiliary gate are provided. The high-voltage MOS transistors include a source region and a drain region provided in a semiconductor substrate. A main gate electrode is disposed over the semiconductor substrate between the drain region and the source region. A lower drain-side auxiliary gate and an upper drain-side auxiliary gate are sequentially stacked over the semiconductor substrate between the main gate electrode and the drain region. The lower drain-side auxiliary gate is electrically insulated from the semiconductor substrate, the main gate electrode and the upper drain-side auxiliary gate. Methods of fabricating the high-voltage MOS transistors are also provided.

Abstract: A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.

Abstract: A non-volatile memory device, including a substrate of a first conductivity type, the substrate including a plurality of wells of a second conductivity type, a plurality of memory cells in one of the plurality of wells of the second conductivity type, and a peripheral circuit including at least one first transistor of the second conductivity type on the substrate, and at least one second transistor of the first conductivity type in another one of the plurality of wells of the second conductivity type.

Abstract: A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors.

Abstract: A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.

Abstract: Methods of forming an electronic device may include forming a gate electrode on a semiconductor substrate, and forming first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode. An insulating layer may be formed on the semiconductor substrate including the first and second impurity doped regions, and first and second holes may be formed in the insulating layer, with the first and second holes respectively exposing portions of the first and second impurity doped regions. In addition, first and second epitaxial semiconductor layers may be formed in the respective first and second holes on the exposed portions of the first and second impurity doped regions of the semiconductor substrate. Related devices are also discussed.

Abstract: A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

Abstract: A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

Abstract: A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.

Abstract: This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers.

Abstract: A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors.

Abstract: A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors.

Abstract: A nonvolatile memory device includes a semiconductor substrate, a device isolation layer, a tunnel insulation layer, a floating gate, a buried floating gate, and a control gate. A trench is in the substrate that defines an active region of the substrate adjacent to the trench. A device isolation layer is on the substrate along the trench. A tunnel insulation layer is on the active region of the substrate. A floating gate is on the tunnel insulation layer opposite to the active region of the substrate. A buried floating gate is on the device isolation layer in the trench. An intergate dielectric layer is on and extends across the floating gate and the buried floating gate. A control gate is on the intergate dielectric layer and extends across the floating gate and the buried floating gate.

Abstract: Provided are semiconductor devices and methods of fabricating the same. A semiconductor device may include a semiconductor substrate with a device isolation layer defining HVE and HVD active regions. Gate insulation layer patterns may be disposed on the HVE and HVD active regions. Gate electrodes may be disposed on the gate insulation layer patterns to intersect the HVE and HVD active regions and the device isolation layer. An ion implantation layer may be disposed on the semiconductor substrate under the gate electrode of the HVD active region, spaced apart from the device isolation layer, and serves to adjust a threshold voltage.

Abstract: Unit cells of silicon-oxide-nitride-oxide-silicon (SONOS) memory devices are provided. The unit cells include an integrated circuit substrate and a SONOS memory cell on the integrated circuit substrate. The SONOS memory cell includes a source region, a drain region and a gate contact. The integrated circuit substrate defines a trench between the source and drain regions and the gate contact is provided in the trench. A floor of the trench extends further into the integrated circuit substrate than lower surfaces of the source and drain regions. Related methods of fabricating SONOS memory cells are also provided.

Abstract: A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

Abstract: An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.