Abstract: An apparatus for generating internal write control signals applicable to a double data rate SDRAM, includes: a first unit for receiving write command signals to generate a write standby signal and an initial column address strobe (CAS) active signal, wherein the write command signal includes a row address strobe (RAS) signal, a column address strobe (CAS) bar signal, a write enable (WE) bar signal, and a chip select (CS) bar signal; a second unit for receiving the write standby signal to generate an input path enable signal; a third unit for receiving the initial CAS (column address strobe) active signal to generate a write CAS active signal and a write shield bar signal; a fourth unit for receiving the write command signals and the write shield bar signal to generate a precharge shield bar signal and a read shield bar signal, wherein the precharge shield bar signal is fed back to an input terminal of the fourth unit and is inputted as another input signal of the second unit; and a fifth unit for receiving th