Abstract: Providing an image combination device and/or a display system comprising the same. The image combination device including an SGL control unit separating a plurality of layers into a first group layer and a second group layer not overlapping the first group layer, and a multi-layer blender combining the first group layer to produce a first composite image in a first frame and combining the second group layer including updated layers with the first composite image of the first frame to produce a second composite image in a second frame subsequent to the first frame.

Abstract: Providing an image combination device and/or a display system comprising the same. The image combination device including an SGL control unit separating a plurality of layers into a first group layer and a second group layer not overlapping the first group layer, and a multi-layer blender combining the first group layer to produce a first composite image in a first frame and combining the second group layer including updated layers with the first composite image of the first frame to produce a second composite image in a second frame subsequent to the first frame.

Abstract: In a display controller for generating a video sync signal using an external clock, he display controller includes an initializer configured to initialize an internal parameter in response to a frame start signal. A sync signal generation circuit is configured to count the external clock, increase the internal parameter, and generate the video sync signal according to a result of comparing the internal parameter that has been increased with a setting value. An original use of the external clock may not be generating the video sync signal.

Abstract: Providing an image combination device and/or a display system comprising the same. The image combination device including an SGL control unit separating a plurality of layers into a first group layer and a second group layer not overlapping the first group layer, and a multi-layer blender combining the first group layer to produce a first composite image in a first frame and combining the second group layer including updated layers with the first composite image of the first frame to produce a second composite image in a second frame subsequent to the first frame.

Abstract: An electronic device includes a processor configured to generate a slice update map indicating a location of at least one updated slice having a data change in frame data including a plurality of slices; and a display controller configured to extract frame data of the at least one updated slice from a memory based on the slice update map and transfer the frame data to a display driver.

Abstract: A data processing system including a shared resource, a first data processing device configured to generate a first resource request signal requesting the shared resource, a second data processing device configured to generate a second resource request signal requesting the shared resource, and a resource manager master configured to receive the first resource request signal and the second resource request signal, check a state of the shared resource, determine whether the first resource request signal or the second resource request signal is received earlier, and output a grant signal to the first data processing devices and a rejection signal to the second data processing device when the first resource request signal is received earlier than the second resource request signal. The first data processing device processes data using the shared resource according to the grant signal.

Abstract: An electronic device includes a processor configured to generate a slice update map indicating a location of at least one updated slice having a data change in frame data including a plurality of slices; and a display controller configured to extract frame data of the at least one updated slice from a memory based on the slice update map and transfer the frame data to a display driver.

Abstract: In a display controller for generating a video sync signal using an external clock, he display controller includes an initializer configured to initialize an internal parameter in response to a frame start signal. A sync signal generation circuit is configured to count the external clock, increase the internal parameter, and generate the video sync signal according to a result of comparing the internal parameter that has been increased with a setting value. An original use of the external clock may not be generating the video sync signal.

Abstract: A data processing system including a shared resource, a first data processing device configured to generate a first resource request signal requesting the shared resource, a second data processing device configured to generate a second resource request signal requesting the shared resource, and a resource manager master configured to receive the first resource request signal and the second resource request signal, check a state of the shared resource, determine whether the first resource request signal or the second resource request signal is received earlier, and output a grant signal to the first data processing devices and a rejection signal to the second data processing device when the first resource request signal is received earlier than the second resource request signal. The first data processing device processes data using the shared resource according to the grant signal.

Abstract: A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to perform second processing on second data in response to receiving a first processing result obtained by performing the first processing on the first data. Performing the second processing is based on second control information stored in a second storage unit. The update control unit is configured to determine an update time of the first control information or an update time of the second control information in response to performing the first processing and performing the second processing.

Abstract: A semiconductor device includes a controller that monitors a first toggle rate of first data and determines a conversion mode for the first data, and a first toggle rate converter that converts the first data into second data having a second toggle rate different from the first toggle rate when the conversion mode is a first mode, and that converts the first data into third data having a third toggle rate different from the first and second toggle rates when the conversion mode is a second mode different from the first mode.

Abstract: A multimedia system includes a main special function register (SFR) configured to store SFR information; a plurality of processing modules each configured to process frames of data, based on the SFR information; and a system control logic configured to control operations of the main SFR and the plurality of processing modules. The plurality of processing modules may process data of different frames at the same time period.

Abstract: Providing an image combination device and/or a display system comprising the same. The image combination device including an SGL control unit separating a plurality of layers into a first group layer and a second group layer not overlapping the first group layer, and a multi-layer blender combining the first group layer to produce a first composite image in a first frame and combining the second group layer including updated layers with the first composite image of the first frame to produce a second composite image in a second frame subsequent to the first frame.

Abstract: A multimedia system includes a main special function register (SFR) configured to store SFR information; a plurality of processing modules each configured to process frames of data, based on the SFR information; and a system control logic configured to control operations of the main SFR and the plurality of processing modules. The plurality of processing modules may process data of different frames at the same time period.

Abstract: A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to perform second processing on second data in response to receiving a first processing result obtained by performing the first processing on the first data. Performing the second processing is based on second control information stored in a second storage unit. The update control unit is configured to determine an update time of the first control information or an update time of the second control information in response to performing the first processing and performing the second processing.