Patents by Inventor Sung-Hoon Ko

Sung-Hoon Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7646051
    Abstract: A semiconductor device includes a semiconductor substrate, a storage pad and a bit line pad on the semiconductor substrate, a first interlayer insulating layer covering the bit line pad and including a bit line contact hole having a width greater than a width of the bit line pad, a barrier insulating layer on sidewalls of the first interlayer insulating layer and upper portions of sidewalls of the bit line pad that are exposed by the bit line contact hole, a bit line plug in the bit line contact hole and on the barrier insulating layer; and a storage plug penetrating the first interlayer insulating layer and contacting the storage pad.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: January 12, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sung-Hoon Ko
  • Publication number: 20070181926
    Abstract: A semiconductor device includes a semiconductor substrate, a storage pad and a bit line pad on the semiconductor substrate, a first interlayer insulating layer covering the bit line pad and including a bit line contact hole having a width greater than a width of the bit line pad, a barrier insulating layer on sidewalls of the first interlayer insulating layer and upper portions of sidewalls of the bit line pad that are exposed by the bit line contact hole, a bit line plug in the bit line contact hole and on the barrier insulating layer; and a storage plug penetrating the first interlayer insulating layer and contacting the storage pad.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 9, 2007
    Inventor: Sung-Hoon Ko
  • Patent number: 6043165
    Abstract: Methods of forming electrically interconnected lines using organic compound cleaning agents include the steps of forming a first electrically conductive line on a substrate and then forming a first electrically insulating layer on the first electrically conductive line to electrically isolate the first conductive line from adjacent regions and lines. An organic spin-on-glass (SOG) passivation layer is then formed as a planarization layer on the first electrically insulating layer. The organic SOG layer is then etched-back to define a first etched surface thereon, using a carbon-fluoride gas which also preferably contains argon. The organic SOG layer may even be sufficiently etched back to expose an upper surface of the first electrically insulating layer. The first etched surface is then exposed to an organic compound cleaning agent so that organic residues can be removed from the etched surface so that layers subsequently formed on the etched surface are less susceptible to lift-off and flaking.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: March 28, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-hun Park, Sung-hoon Ko, Jong-seob Lee