Abstract: A photonic sensor includes a first electrode layer, a second electrode layer, a third electrode layer, a first photon absorption layer, a second photon absorption layer, a third photon absorption layer and a charge blocking layer. The first photon absorption layer includes a dispersion of first nanoparticles, and is configured to transduce a first colored light into corresponding electric charge. The second photon absorption layer includes a dispersion of second nanoparticles, and is configured to transduce a second colored light into corresponding electric charge according to light intensity. The third photon absorption layer includes a dispersion of third nanoparticles, and is configured to transduce a third colored light into corresponding electric charge according to light intensity. The charge blocking layer is formed between the first and second photon absorption layers to block flow of electric charge between the first and second photon absorption layers.

Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.

Abstract: A display device includes a lower panel including a lower substrate and a pixel transistor formed on the lower substrate; and an upper panel facing the lower panel, and including an upper substrate, a sensing transistor formed on the upper substrate, and a readout transistor connected to the sensing transistor and transmitting a signal. The readout transistor includes a first lower gate electrode formed on the upper substrate, a first semiconductor layer formed on the first lower gate electrode and overlaps the first gate electrode, and a first source electrode and a first drain electrode disposed on the first semiconductor layer.

Abstract: The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.

Abstract: A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.

Abstract: An array substrate includes a base substrate which includes a display area and a peripheral area adjacent to the display area, a plurality of fan-out lines arranged in the peripheral area to receive a driving signal from an exterior source, at least one fan-out line among the plurality of fan-out lines arranged on a different layer from a layer on which remaining fan-out lines of the plurality of fan-out lines are arranged, a plurality of signal lines arranged in the display area to receive the driving signal from the plurality of fan-out lines and a pixel array arranged in the display area to receive the driving signal from the plurality of signal lines.

Abstract: In a visible-light blocking member, an infrared sensor including the visible-light blocking member, and a liquid crystal display including the infrared sensor, a visible-light blocking member is a structure including amorphous germanium or a compound of amorphous germanium and has higher transmittance for a wavelength of an infrared ray region than for a wavelength of a visible light region. Accordingly, sensitivity to infrared rays may be increased by applying the visible-light blocking member to the infrared sensor.

Abstract: In a sensing device and a method for sending a light by using the same, the sensing device includes: a lower panel; an upper panel facing the lower panel; a liquid crystal layer disposed between the lower panel and the upper panel; an infrared ray sensor formed in at least one of the lower panel and the upper panel; and a visible ray sensor formed in at least one of the lower panel and the upper panel. The sensing device simultaneously includes the infrared ray sensor and the visible ray sensor such that a touch sensing function or an image sensing function having high reliability may be realized.

Abstract: A display panel that includes: a substrate, a sensing transistor disposed on the substrate, and a readout transistor connected to the sensing transistor and transmitting a detecting signal is presented. The sensing transistor includes a semiconductor layer disposed on the upper substrate, a source electrode and a drain electrode disposed on the semiconductor layer, and a gate electrode overlapping the semiconductor layer on the source electrode and the drain electrode. Accordingly, in a display device and a manufacturing method thereof, an infrared sensing transistor, a visible light sensing transistor, and a readout transistor are simultaneously formed with a top gate structure such that the number of manufacturing processes and the manufacturing cost may be reduced.

Abstract: Provided is a thin-film transistor (TFT) display panel having improved electrical and reliability properties and a method of fabricating the TFT display panel. The TFT display panel includes gate wiring formed on a substrate; an oxide active layer pattern formed on the gate wiring; data wiring formed on the oxide active layer pattern to cross the gate wiring; a passivation layer formed on the oxide active layer pattern and the data wiring and made of nitrogen oxide; and a pixel electrode disposed on the passivation layer.

Abstract: A display substrate includes; a substrate, a gate electrode arranged on the substrate, a semiconductor pattern arranged on the gate electrode, a source electrode arranged on the semiconductor pattern, a drain electrode arranged on the semiconductor pattern and spaced apart from the source electrode, an insulating layer arranged on, and substantially covering, the source electrode and the drain electrode to cover the source electrode and the drain electrode, a conductive layer pattern arranged on the insulating layer and overlapped aligned with the semiconductor pattern, a pixel electrode electrically connected to the drain electrode, and a storage electrode arranged on the substrate and overlapped overlapping with the pixel electrode, the storage electrode being electrically connected to the conductive layer pattern.

Abstract: A display substrate includes respective pluralities of gate lines, data lines, switching elements, storage lines, pixel electrodes, and an organic insulation layer. The gate lines and the data lines define a plurality of unit pixels. The storage lines are respectively formed adjacent to the respective drain electrodes of the respective switching elements of respective rows of the unit pixels. The organic insulation layer has a hole that is formed within the area of each of the unit pixels and that extends from a contact area formed at a portion of the corresponding drain electrode of the pixel to a portion corresponding to the storage line thereof. This arrangement enables the marginal area needed to prevent mismatch of the hole in the areas of the contact area and the storage line to be reduced, thereby increasing the aperture ratio of the display.

Abstract: In a liquid crystal display device, the device includes a first substrate, a second substrate and a liquid crystal layer interposed therebetween. The first substrate includes a pixel electrode, a thin film transistor connected to the pixel electrode, and also a hitch to connect both a lower and upper electrode of the pixel electrode. The second substrate includes a common electrode having a lower domain division part and an upper domain division part, in which each of domain division part is formed at the position corresponding to the lower and upper electrode of the pixel electrode, respectively. Through the electric field controller connected at both sides of the upper electrode of the pixel electrode, quality of display image can improve without a darkening area occurring at one part of the unit pixel.

Abstract: A panel assembly includes a gate wire, a data wire, a plurality of pixel electrodes, a liquid crystal layer, and a common electrode. The gate wire includes a plurality of gate lines and the data wire includes a plurality of data lines crossing and insulated from the gate lines. The pixel electrodes are insulated from each other and disposed on the data wire. The liquid crystal layer is disposed on the pixel electrodes and includes liquid crystal molecules, and a common electrode is disposed on the liquid crystal layer. The gate lines cross a center of the pixel electrodes, and the common electrode includes a plurality of cutting patterns that overlap the gate lines.

Abstract: In a liquid crystal display (LCD) apparatus and a method for manufacturing the LCD apparatus, the LCD apparatus includes first and second substrates, and a liquid crystal layer disposed between the first and second substrates. The first substrate includes a transparent insulating substrate, a conductive layer formed over an entire surface of the transparent insulating substrate, and a transparent conductive electrode formed on the conductive layer.

Abstract: A fan-out unit which can control a resistance difference among channels with efficient space utilization and a thin-film transistor (TFT) array substrate having the fan-out unit are presented. The fan-out unit includes: an insulating substrate; a first wiring layer which is formed on the insulating substrate and connected to a pad; a second wiring layer which is formed on the insulating substrate and connected to a TFT; and a resistance controller which is connected between the first wiring layer and the second wiring layer and includes a plurality of first resistors extending parallel to the first wiring layer and a plurality of second resistors extending perpendicular to the first resistors and alternately connecting to the first resistors, wherein the first resistors are longer than the second resistors.

Abstract: Provided is a method for manufacturing a thin-film transistor substrate, in which the etching characteristics of an insulating film and a passivation layer are enhanced. The insulating film and the passivation layer are deposited by low temperature chemical vapor deposition. The method includes disposing a gate wiring on an insulating substrate; disposing a gate insulating film on the gate wiring; disposing a data wiring on the gate insulating film; disposing a passivation layer on the data wiring; and forming a contact hole by etching at least one of the gate insulating film and the passivation layer, wherein at least one of the gate insulating film and the passivation layer is disposed at a temperature of about 280° C. or below, and the forming of the contact hole is performed at a pressure of about 60 mT or below.

Abstract: A thin film transistor array panel including a substrate, gate lines formed on the substrate and extending in a first direction, data lines formed on the substrate and extending in a second direction, wherein the data lines cross and are insulated from the gate lines, and thin film transistors each with a control terminal, an input terminal, and an output terminal. The control and input terminals of the thin film transistor are connected to the gate and data lines. A barrier rib is formed on the gate lines, the data lines, and the thin film transistors. The barrier rib has the same pattern as the gate lines, the data lines, and the thin film transistors. Color filters fill regions demarcated by the barrier rib. Pixel electrodes are formed on the color filters. The output terminal of the thin film transistor has an opening, and a portion of the barrier rib formed on the output terminal has an output opening. The barrier rib output terminal portion has the same pattern as the output terminal.

Abstract: A liquid crystal display includes; a first substrate, a gate line and a data line disposed on the first substrate, a color filter including protrusions and depressions aligned with the data line, the color filter being disposed on the data line, a pixel electrode disposed on the color filter, a second substrate facing the first substrate, a common electrode disposed on the second substrate, and a liquid crystal layer interposed between the first substrate and the second substrate.

Abstract: A method of manufacturing a silicon layer includes pretreating a surface of a silicon nitride layer formed on a substrate through a plasma enhanced chemical vapor deposition method using a first reaction gas including at least one of silicone tetrafluoride (SiF4) gas, a nitrogen trifluoride (NF3) gas, SiF4—H2 gas and a mixture thereof. Then, a silicon layer is formed on the pretreated silicon nitride layer through the plasma enhanced chemical vapor deposition method using a second reaction gas including a mixture of gas including silicon tetrafluoride (SiF4), hydrogen (H2) and argon (Ar).