Patents by Inventor Sung-Hsiung Wang
Sung-Hsiung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7968968Abstract: An inductor utilizing a pad metal layer. The inductor comprises a metal spiral, a metal bridge, and a metal interconnect. The metal bridge is formed with the pad metal layer and a plurality of vias and has one end connected to the metal spiral. The metal interconnect is connected to the other end of the metal bridge. In addition, resistivity of the pad metal layer is lower than that of the metal spiral.Type: GrantFiled: May 28, 2010Date of Patent: June 28, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sung-Hsiung Wang, Chih-Ping Chao, Chia-Yu Su
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Publication number: 20100265025Abstract: An inductor utilizing a pad metal layer. The inductor comprises a metal spiral, a metal bridge, and a metal interconnect. The metal bridge is formed with the pad metal layer and a plurality of vias and has one end connected to the metal spiral. The metal interconnect is connected to the other end of the metal bridge. In addition, resistivity of the pad metal layer is lower than that of the metal spiral.Type: ApplicationFiled: May 28, 2010Publication date: October 21, 2010Inventors: Sung-Hsiung Wang, Chih-Ping Chao, Chia-Yu Su
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Publication number: 20080122029Abstract: An inductor utilizing a pad metal layer. The inductor comprises a metal spiral, a metal bridge, and a metal interconnect. The metal bridge is formed with the pad metal layer and a plurality of vias and has one end connected to the metal spiral. The metal interconnect is connected to the other end of the metal bridge. In addition, resistivity of the pad metal layer is lower than that of the metal spiral.Type: ApplicationFiled: November 3, 2006Publication date: May 29, 2008Inventors: Sung-Hsiung Wang, Chih-Ping Chao, Chia-Yi Su
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Patent number: 7297629Abstract: Novel dual damascene methods characterized by short cycle time and low expense. In one embodiment, the method includes providing a dielectric layer on a substrate; etching a via in the dielectric layer; filling the via with a conductive metal such as copper; providing a second dielectric layer over the via; etching a trench in the second dielectric layer; and filling the trench with a conductive metal such as copper. In another embodiment, the method includes providing a dielectric layer on a substrate; etching a partial via in the dielectric layer; etching a partial trench in the dielectric layer over the partial via; completing the via and the trench in a single etching step; and filling the via and the trench with a conductive metal such as copper to complete the via and metal line, respectively.Type: GrantFiled: September 15, 2004Date of Patent: November 20, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Sung-Hsiung Wang
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Patent number: 7229879Abstract: A microelectronic product and a method for fabricating the same each provide a capacitor formed interposed between a first dielectric layer and a second dielectric layer formed over a substrate having a first contact region and a second contact region exposed therein. The capacitor is also connected to a first conductor stud that penetrates the first dielectric layer and contacts the first contact region and a second conductor stud that penetrates the second dielectric layer. A contiguous conductor interconnect and conductor stud layer is formed within a dual damascene aperture through the second dielectric layer and the first dielectric layer and contacting the second contact region. An etch stop layer employed when forming a trench within the dual damascene aperture also passivates a capacitor sidewall.Type: GrantFiled: November 22, 2005Date of Patent: June 12, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Sung Hsiung Wang
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Patent number: 7074721Abstract: A method for forming a void free ultra thick dual damascene copper feature providing a semiconductor process wafer comprising via openings formed in a first undoped silicate glass (USG) layer the first USG layer having an overlying a second USG layer formed having a thickness of greater than about 1 micron and an overlying silicon oxynitride BARC layer; forming a trench opening having a width of greater than about 1 micron to encompass one of the via openings; forming a barrier layer to line the dual damascene opening; forming a copper seed layer having a thickness of from about 1000 Angstroms to about 2000 Angstroms; carrying out a multi-step electrochemical deposition (ECD); and, carrying out a two step copper annealing process.Type: GrantFiled: April 3, 2003Date of Patent: July 11, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Sung-Hsiung Wang
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Patent number: 7038266Abstract: A microelectronic product and a method for fabricating the same each provide a capacitor formed interposed between a first dielectric layer and a second dielectric layer formed over a substrate having a first contact region and a second contact region exposed therein. The capacitor is also connected to a first conductor stud that penetrate4s the first dielectric layer and contacts the first contact region and a second conductor stud that penetrates the second dielectric layer. A contiguous conductor interconnect and conductor stud layer is formed within a dual damascene aperture through the second dielectric layer and the first dielectric layer and contacting the second contact region. An etch stop layer employed when forming a trench within the dual damascene aperture also passivates a capacitor sidewall.Type: GrantFiled: March 1, 2004Date of Patent: May 2, 2006Assignee: Taiwan Semiconductor Manufacturing Co LtdInventor: Sung Hsiung Wang
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Publication number: 20060057842Abstract: Novel dual damascene methods characterized by short cycle time and low expense. In one embodiment, the method includes providing a dielectric layer on a substrate; etching a via in the dielectric layer; filling the via with a conductive metal such as copper; providing a second dielectric layer over the via; etching a trench in the second dielectric layer; and filling the trench with a conductive metal such as copper. In another embodiment, the method includes providing a dielectric layer on a substrate; etching a partial via in the dielectric layer; etching a partial trench in the dielectric layer over the partial via; completing the via and the trench in a single etching step; and filling the via and the trench with a conductive metal such as copper to complete the via and metal line, respectively.Type: ApplicationFiled: September 15, 2004Publication date: March 16, 2006Inventor: Sung-Hsiung Wang
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Patent number: 6903644Abstract: An inductor device including a first coil conductor (310) and a second coil conductor (510), the first coil conductor (310) being located over a substrate (120) and having a first pattern and a first conductivity, and the second coil conductor (510) being located on a substantial portion of the first coil conductor (310), having a second pattern substantially conforming to the first pattern, and having a second conductivity substantially greater than the first conductivity.Type: GrantFiled: July 28, 2003Date of Patent: June 7, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Hsiung Wang, Shuo-Mao Chen, Heng-Ming Hsu, Jui-Feng Kuan, Chih-Ping Chao, Chih-Hsien Lin
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Publication number: 20050024176Abstract: An inductor device including a first coil conductor (310) and a second coil conductor (510), the first coil conductor (310) being located over a substrate (120) and having a first pattern and a first conductivity, and the second coil conductor (510) being located on a substantial portion of the first coil conductor (310), having a second pattern substantially conforming to the first pattern, and having a second conductivity substantially greater than the first conductivity.Type: ApplicationFiled: July 28, 2003Publication date: February 3, 2005Inventors: Sung-Hsiung Wang, Shuo-Mao Chen, Heng-Ming Hsu, Jui-Feng Kuan, Chih-Ping Chao, Chih-Hsien Lin
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Publication number: 20040198055Abstract: A method for forming a void free ultra thick dual damascene copper feature providing a semiconductor process wafer comprising via openings formed in a first undoped silicate glass (USG) layer the first USG layer having an overlying a second USG layer formed having a thickness of greater than about 1 micron and an overlying silicon oxynitride BARC layer; forming a trench opening having a width of greater than about 1 micron to encompass one of the via openings; forming a barrier layer to line the dual damascene opening; forming a copper seed layer having a thickness of from about 1000 Angstroms to about 2000 Angstroms; carrying out a multi-step electrochemical deposition (ECD); and, carrying out a two step copper annealing process.Type: ApplicationFiled: April 3, 2003Publication date: October 7, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Sung-Hsiung Wang
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Patent number: 6617234Abstract: A method of forming metal fuses and bonding pads. A conductive layer is formed in a substrate. A dielectric layer is formed over the substrate. The dielectric layer has an opening that exposes a portion of the conductive layer. A metallic layer is formed over the dielectric layer. The metallic layer is patterned to form a metal fuse and a bonding pad. The bonding pad is electrically connected to the conductive layer via the opening. Both the metal fuse and the bonding pad have undercut sidewalls. Spacers are formed on the undercut sidewalls of the metal fuse and the bonding pad. Finally, a passivation layer that exposes the metal fuse and the bonding pad is formed over the substrate.Type: GrantFiled: April 13, 2001Date of Patent: September 9, 2003Assignee: United Microelectronics Corp.Inventors: Sung-Hsiung Wang, Yimin Huang, Chiung-Sheng Hsiung
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Patent number: 6583489Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.Type: GrantFiled: March 25, 2002Date of Patent: June 24, 2003Assignee: United Microelectronics Corp.Inventors: Sung-Hsiung Wang, Yi-Min Huang, Gwo-Shii Yang, Chiung-Sheng Hsiung, Hsueh-Chung Chen, Chih-Chien Liu
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Patent number: 6559004Abstract: A method for forming a three dimensional semiconductor structure which has vertical capacitor(s) but not horizontal capacitor(s). The method essentially at least includes these steps of forming bottom plates within dielectric layers, forming another dielectric layer over bottom plates, removing all dielectric layers over bottom plates, forming optional liner(s) and capacitor dielectric layers on bottom plates, and forming top plates over capacitor dielectric layers. Note that shape of bottom plates is alike to the bottom connection and verticle fingers, also note that each gap within bottom plates is filled by both capacitor dielectric layer and top plate.Type: GrantFiled: December 11, 2001Date of Patent: May 6, 2003Assignee: United Microelectronics Corp.Inventors: Gwo-Shii Yang, Hsueh-Chung Chen, Chiung-Sheng Hsiung, Tong-Yu Chen, Sung-Hsiung Wang
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Publication number: 20030020163Abstract: A bonding pad structure for copper/low-k dielectric material back end of the line (BEOL) processes is disclosed. The bonding pad structure uses a dielectric layer and a conductive pad formed by a gap fill process to protect the underlying bonding pad structure. The conductive pad has a plurality of via plugs in the dielectric layer connecting the underlying bonding pad structure. The bonding pad structure also has a passivation layer having a pad window with a smooth contour to expose the conductive pad.Type: ApplicationFiled: July 25, 2001Publication date: January 30, 2003Inventors: Cheng-Yu Hung, Sung-Hsiung Wang, Kun-Chih Wang
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Publication number: 20020155261Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.Type: ApplicationFiled: April 24, 2001Publication date: October 24, 2002Inventors: Sung-Hsiung Wang, Yi-Min Huang, Gwo-Shii Yang, Chiung-Sheng Hsiung, Hsueh-Chung Chen, Chih-Chien Liu
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Publication number: 20020155263Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.Type: ApplicationFiled: March 25, 2002Publication date: October 24, 2002Applicant: United Microoelectronics Corp.Inventors: Sung-Hsiung Wang, Yi-Min Huang, Gwo-Shii Yang, Chiung-Sheng Hsiung, Hsueh-Chung Chen, Chih-Chien Liu
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Publication number: 20020155672Abstract: A method of forming metal fuses. A conductive layer is formed in a substrate. A dielectric layer is formed over the substrate. The dielectric layer has an opening that exposes a portion of the conductive layer. A metallic layer is formed over the dielectric layer. The metallic layer is patterned to form a metal fuse and a bonding pad. The bonding pad is electrically connected to the conductive layer via the opening. Both the metal fuse and the bonding pad have undercut sidewalls. Spacers are formed on the undercut sidewalls of the metal fuse and the bonding pad. Finally, a passivation layer that exposes the metal fuse and the bonding pad is formed over the substrate.Type: ApplicationFiled: April 13, 2001Publication date: October 24, 2002Inventors: Sung-Hsiung Wang, Yimin Huang, Chiung-Sheng Hsiung
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Patent number: 6417096Abstract: A substrate is provided. A first dielectric layer is formed over the substrate by deposition. Etching stop layer and a second dielectric layer are formed in turn over the first dielectric. Next, the second dielectric layer is dealt with Lewis acid. Then, a first photoresist layer is defined and formed over the second dielectric layer. And then dry etching is carried out by means of the first photoresist layer as the mask to form a via hole. The surface of the second dielectric layer and the via hole are treated with Lewis acid. Subsequently, the second photoresist layer is defined and formed on the second dielectric layer. Dry etching is proceed, and etching stop layer is as a etching terminal point to remove exposed partial surface of the second dielectric layer so as to form a trench having larger horizontal size than the via hole. Subsequently, the second photoresist layer is removed to form the opening of the damascene.Type: GrantFiled: July 7, 2000Date of Patent: July 9, 2002Assignee: United Microelectronics Corp.Inventors: Anseime Chen, Jun Maeda, Sheng-Yueh Chang, Sung-Hsiung Wang
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Patent number: 6355568Abstract: A cleaning method for a copper dual damascene process, applicable for cleaning a structure having a dual damascene opening. The method begins with preparing a first chemical solution and a second chemical solution. The first chemical solution includes a deionized water, a hydrogen peroxide, and a surfactant, whereas the second chemical solution includes a deionized water, a hydrogen fluoride, and a hydrogen chloride. A first cleaning step is performed using the first chemical solution to remove particles and polymers that remain on a surface of a copper layer and the dual damascene opening. This is followed by performing a second cleaning step using the second chemical solution to remove a copper oxide layer on the copper layer.Type: GrantFiled: May 26, 2000Date of Patent: March 12, 2002Assignee: United Microelectronics Corp.Inventors: Sung-Hsiung Wang, Chan-Lon Yang