Abstract: There is provided a backlight unit having a protection circuit using a center-tap, the backlight unit including: a current balancing unit including a plurality of primary coils individually transmitting the lamp driving power from an inverter unit to the lamps, and a plurality of secondary coils each formed of one conductor having a center-tap, and receiving an electromagnetically induced voltage from each of the plurality of primary coils, the one end and the center-tap of each of the plurality of secondary coils connected in series with the one end and the center-tap of the neighboring secondary coil to form at least one closed loop and maintain current transmitted to each of the lamps balanced; a sensing unit sensing a variation in current of the closed loop and a variation in current of the primary coil from the current balancing unit; and a determination unit determining whether each of the lamps performs an abnormal operation or not.

Abstract: There is provided a backlight unit that determines whether a lamp performs an abnormal operation by detecting a voltage that is induced in a power conversion transformer without using a complicated and expensive detection circuit. A backlight unit having a protection circuit using induced voltage detection according to an aspect of the invention includes an inverter part including a primary coil receiving power and at least one secondary coil converting the power from the primary coil to AC power set beforehand, a lamp part including at least one lamp receiving the AC power from the inverter part to emit light, a detection part including conductors detecting voltages electromagnetically induced in the secondary coil, and an abnormality determining part comparing detection voltages from the detection part with a reference voltage set beforehand.

Abstract: A clock circuit. The clock circuit includes a phase detector and an output unit. The phase detector is coupled to receive a reference clock signal and an output clock signal, and is configured to provide a phase signal indicative of a phase difference between the reference and output clock signals. The output unit is configured to provide the output clock signal, and is coupled to a first supply voltage node and a second supply voltage node. The output unit includes a biasing circuit and a voltage-controlled element. The biasing circuit is coupled to receive a control voltage based on the phase signal and is configured to generate a bias voltage based on the received control voltage. The voltage-controlled element is configured to adjust a parameter of the output clock signal based on the bias voltage. A supply-independent output clock is attained using this configuration.

Abstract: A liquid crystal display device having variable viewing angles includes a first liquid crystal cell having first and second substrates spaced apart from and facing each other, a pixel electrode formed on an inner surface of the first substrate, a common electrode formed on an inner surface of the second substrate, and a first liquid crystal layer interposed between the pixel electrode and the common electrode; a second liquid crystal cell on the first liquid crystal cell, the second liquid crystal cell having third and fourth substrates spaced apart from and facing each other, and two alignment layers, wherein the first and second alignment layers are arranged to have holographic patterns; and a switching part for selectively applying electric field to the second liquid crystal.

Abstract: A clock circuit. The clock circuit includes a phase detector and an output unit. The phase detector is coupled to receive a reference clock signal and an output clock signal, and is configured to provide a phase signal indicative of a phase difference between the reference and output clock signals. The output unit is configured to provide the output clock signal, and is coupled to a first supply voltage node and a second supply voltage node. The output unit includes a biasing circuit and a voltage-controlled element. The biasing circuit is coupled to receive a control voltage based on the phase signal and is configured to generate a bias voltage based on the received control voltage. The voltage-controlled element is configured to adjust a parameter of the output clock signal based on the bias voltage. A supply-independent output clock is attained using this configuration.

Abstract: An apparatus that minimizes phase error and jitter in a phase-locked loop. The apparatus includes a phase/frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider, which are coupled together to form a phase-locked loop. The charge pump within the phase-locked loop contains a pull-up network and a pull-down network which are coupled to each other, and a current compensation device. If the pull-up network and the pull-down network are both conducting, the current compensation device adjusts currents flowing through the pull-up network and through the pull-down network such that the currents are substantially equal. This ensures that very little current flows into the loop filter, thereby substantially minimizing a build-up of charge on a capacitor in the loop filter, which can cause phase error and jitter in the phase-locked loop.

Abstract: A liquid crystal display device having variable viewing angles includes a first liquid crystal cell having first and second substrates spaced apart from and facing each other, a pixel electrode formed on an inner surface of the first substrate, a common electrode formed on an inner surface of the second substrate, and a first liquid crystal layer interposed between the pixel electrode and the common electrode; a second liquid crystal cell on the first liquid crystal cell, the second liquid crystal cell having third and fourth substrates spaced apart from and facing each other, and two alignment layers, wherein the first and second alignment layers are arranged to have holographic patterns; and a switching part for selectively applying electric field to the second liquid crystal.

Abstract: A liquid crystal display device having variable viewing angles includes a first liquid crystal cell having first and second substrates spaced apart from and facing each other, a pixel electrode formed on an inner surface of the first substrate, a common electrode formed on an inner surface of the second substrate, and a first liquid crystal layer interposed between the pixel electrode and the common electrode; a second liquid crystal cell on the first liquid crystal cell, the second liquid crystal cell having third and fourth substrates spaced apart from and facing each other, and two alignment layers, wherein the first and second alignment layers are arranged to have holographic patterns; and a switching part for selectively applying electric field to the second liquid crystal.

Abstract: In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.

Abstract: An array substrate for use in a liquid crystal display device is fabricated by the steps of forming a buffer layer on a substrate; forming a polycrystalline-silicon active layer on the buffer layer, the said active layer having an island shape; forming a gate insulation layer on the buffer layer to cover the polycrystalline-silicon active layer; forming a first metal layer on the gate insulation layer; forming a second metal layer on the first metal layer; patterning the first and second metal layer to form a gate electrode, a gate line and a gate shorting bar; forming a source contact area and a drain contact area at both sides of the polycrystalline-silicon active layer; forming an interlayer insulator on the gate insulation layer to cover the patterned first and second metal layers; patterning the interlayer insulator and the gate insulation layer so as to form a first contact hole to the source contact area and the second contact hole to a drain contact area, patterning a portion of the interlayer insulat

Abstract: A liquid crystal display device having variable viewing angles includes a first liquid crystal cell having first and second substrates spaced apart from and facing each other, a pixel electrode formed on an inner surface of the first substrate, a common electrode formed on an inner surface of the second substrate, and a first liquid crystal layer interposed between the pixel electrode and the common electrode; a second liquid crystal cell on the first liquid crystal cell, the second liquid crystal cell having third and fourth substrates spaced apart from and facing each other, and two alignment layers, wherein the first and second alignment layers are arranged to have holographic patterns; and a switching part for selectively applying electric field to the second liquid crystal.

Abstract: In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.

Abstract: A clock buffer circuit is disclosed. The clock buffer circuit is included in each sub-block of a clock distribution structure in an integrated circuit. Each clock buffer circuit comprises a plurality of driving inverters, and each clock buffer circuit presents an equal input load to the previous driver, regardless of the amount of load in the sub-block circuit. In each sub-block, the clock buffer circuit is connected to provide an output including the combined signals of a portion of the inverters. The portion is approximated by the load of the circuit in the sub-block divided by the load of the circuit in the sub-block having the greatest load of any sub-block. The outputs of inverters not connected to the load of the sub-block circuit are wired to power and ground terminals. Each driving inverter may comprise a pMOS FET paired with an nMOS FET. A method for designing such a clock buffer circuit is also disclosed.

Abstract: An improved output driver that minimizes source point reflections when driving a signal on a transmission line by generating a constant source impedance. The improved output driver uses a transistor switching circuit for generating a nearly constant channel impedance when transistor switching circuit is enabled and is not operating in a saturation mode. A switched diode circuit is coupled in parallel to the transistor switching circuit for generating a nearly constant source impedance when a sufficient voltage to bias the switch diode circuit is applied. Control circuitry is coupled to both the transistor switching circuit and to the switched diode circuit for enabling and disabling the transistor switching circuit and the switched diode circuit. By alternatively enabling and disabling the transistor switching circuit and the switched diode circuit the control circuit is able to generate a constant source impedance.

Abstract: The present invention relates to a process control monitoring system and method. The system and method uses current comparator circuits for monitoring process changes. Process sensitive current sources are compared with weighted reference current sources in a manner that each output of the current comparators demonstrates the inequality of the current sources. By setting the weighted reference current sources properly, the outputs of the current comparators may be used to locate the process corner of the fabricated integrated circuit.

Abstract: A phase-frequency detector for a phase-locked loop (PLL) circuit has symmetrical phase detection characteristics and produces symmetrical activation times on the "up" and "down" outputs for connection to a PLL charge pump circuit. The symmetrical characteristics are accomplished by using RS latch circuits at the outputs of the phase-frequency detector to provide the same loads and the same propagation delay for both the "up" and the "down" outputs. In addition, cross-wired sequential gates are used for at least some of the gates in the logic gate array of the detector to produce the same propagation delays in the gates.

Abstract: The present invention relates to a power reduction digital-to-analog (DA) converter current source cell. The power reduction DA converter current source cell is comprised of a DA current source cell for sending a current to a current steering matrix and a switching means coupled to the DA current source cell for dynamically controlling the power dissipation of the DA converter current source cell when the current is not required.

Abstract: The present invention relates to a system for neutralizing charge injection problems in a switched current system. The system is comprised of a PMOS transistor coupled in parallel with an NMOS switch transistor. If the channel area of the PMOS transistor and the NMOS transistor are equal, then the clock signal to the PMOS transistor must be adjusted to neutralize the negative channel charges of the NMOS transistor. However, if the clock signal to both the PMOS transistor and the NMOS transistor are equal, then the dimension of the PMOS transistor must be smaller than the NMOS transistor in order to neutralize the negative channel charges of the NMOS transistor.

Abstract: A programmable output pad is disclosed that reduces ground bounce noise and power supply noise under different power supply values and under different load conditions. The programmable output pad comprises a pre-driver, a driver, and a controllable delay. The pre-driver transfers a signal from the input of the output pad to the driver which, in turn, transfers the signal from the pre-driver to an output of the output pad. The controllable delay provides one or more resistors, transistors, transmission gates, or equivalents thereof at the input of the driver which are controlled in order to provide a plurality of different time delays. By selecting these different time delays, the activation of the driver is delayed by different amounts of time. For a given power supply value and load condition, selection of the proper delay effectively reduces both the ground bounce noise on the ground supply of the programmable output pad and the noise on the power supply of the programmable output pad.