Patents by Inventor Sung-Hung CHIANG

Sung-Hung CHIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device package
    Patent number: 11776863
    Abstract: A semiconductor device package includes a carrier, a first interposer disposed and a second interposer. The second interposer is stacked on the first interposer, and the first interposer is mounted to the carrier. The combination of the first interposer and the second interposer is substantially T-shaped.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: October 3, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hao-Chih Hsieh, Tun-Ching Pi, Sung-Hung Chiang, Yu-Chang Chen
  • SEMICONDUCTOR DEVICE PACKAGE
    Publication number: 20220415810
    Abstract: A semiconductor device package includes a number of interposers mounted to the carrier, wherein the number of interposers may be arranged in an irregular pattern.
    Type: Application
    Filed: September 6, 2022
    Publication date: December 29, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hao-Chih HSIEH, Tun-Ching PI, Sung-Hung CHIANG, Yu-Chang CHEN
  • Semiconductor device package
    Patent number: 11437322
    Abstract: A semiconductor device package includes a number of interposers mounted to the carrier, wherein the number of interposers may be arranged in an irregular pattern.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 6, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hao-Chih Hsieh, Tun-Ching Pi, Sung-Hung Chiang, Yu-Chang Chen
  • SEMICONDUCTOR DEVICE PACKAGE
    Publication number: 20210375706
    Abstract: A semiconductor device package includes a carrier, a first interposer disposed and a second interposer. The second interposer is stacked on the first interposer, and the first interposer is mounted to the carrier. The combination of the first interposer and the second interposer is substantially T-shaped.
    Type: Application
    Filed: August 17, 2021
    Publication date: December 2, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hao-Chih HSIEH, Tun-Ching PI, Sung-Hung CHIANG, Yu-Chang CHEN
  • Semiconductor device package
    Patent number: 11094602
    Abstract: A semiconductor device package includes a carrier, a first interposer disposed and a second interposer. The second interposer is stacked on the first interposer, and the first interposer is mounted to the carrier. The combination of the first interposer and the second interposer is substantially T-shaped.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: August 17, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hao-Chih Hsieh, Tun-Ching Pi, Sung-Hung Chiang, Yu-Chang Chen
  • SEMICONDUCTOR DEVICE PACKAGE
    Publication number: 20210043527
    Abstract: A semiconductor device package includes a carrier, a first interposer disposed and a second interposer. The second interposer is stacked on the first interposer, and the first interposer is mounted to the carrier. The combination of the first interposer and the second interposer is substantially T-shaped.
    Type: Application
    Filed: August 9, 2019
    Publication date: February 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hao-Chih HSIEH, Tun-Ching PI, Sung-Hung CHIANG, Yu-Chang CHEN
  • SEMICONDUCTOR DEVICE PACKAGE
    Publication number: 20200083172
    Abstract: A semiconductor device package includes a number of interposers mounted to the carrier, wherein the number of interposers may be arranged in an irregular pattern.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 12, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hao-Chih HSIEH, Tun-Ching PI, Sung-Hung CHIANG, Yu-Chang CHEN
  • Semiconductor device package including filling mold via
    Patent number: 10381300
    Abstract: A semiconductor device package includes a substrate, a package body, a via and an interconnect. The substrate includes a surface and a pad on the first surface. The package body covers at least a portion of the surface of the substrate. The via is disposed in the package body and includes a conductive layer and a first intermediate layer. The conductive layer is electrically connected with the pad. The first intermediate layer is adjacent to the conductive layer. The interconnect is disposed on the first intermediate layer.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: August 13, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jen-Chieh Kao, Chang-Lin Yeh, Yi Chen, Sung-Hung Chiang
  • SEMICONDUCTOR DEVICE PACKAGE INCLUDING FILLING MOLD VIA
    Publication number: 20180151485
    Abstract: A semiconductor device package includes a substrate, a package body, a via and an interconnect. The substrate includes a surface and a pad on the first surface. The package body covers at least a portion of the surface of the substrate. The via is disposed in the package body and includes a conductive layer and a first intermediate layer. The conductive layer is electrically connected with the pad. The first intermediate layer is adjacent to the conductive layer. The interconnect is disposed on the first intermediate layer.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Inventors: Jen-Chieh KAO, Chang-Lin YEH, Yi CHEN, Sung-Hung CHIANG