Abstract: An IoT-based system for measurement of contamination distribution of contaminated groundwater through real-time monitoring of a contamination degree of a contaminated groundwater well for control of a contaminated groundwater purification device and prediction of a purification period based on the measurement result.

Abstract: A scan driver includes: a first transistor having a first electrode coupled to an output scan line, a second electrode coupled to a first power line, and a gate electrode coupled to a first node; a second transistor having a first electrode coupled to a first clock line, a second electrode coupled to the output scan line, and a gate electrode coupled to a second node; a third transistor having a first electrode coupled to the first node, a second electrode coupled to a first input scan line, and a gate electrode coupled to a second clock line; and a fourth transistor having a first electrode coupled to the second node and a second electrode and a gate electrode, which are coupled to a second input scan line, wherein the first input scan line and the second input scan line are different from each other.

Abstract: Disclosed is an interface system including a first neuron cluster that outputs a first neuron signal including a first neuron request and first neuron data by performing a first arithmetic operation, and a first interface circuit that stores the first neuron data and outputs a first response, in response to the first neuron request. The first neuron cluster outputs a second neuron signal including a second neuron request and second neuron data by performing a second arithmetic operation, in response to the first response. Before the first data is transmitted to a second neuron cluster different from the first neuron cluster, the first interface circuit outputs the first response in response to a fact that the first neuron data is stored.

Abstract: Disclosed is an amplification circuit, which includes a first amplifier that receives an external signal and performs first band pass filtering on the external signal to output a first filter signal, and a second amplifier that receives the first filter signal and performs second band pass filtering on the first filter signal to output a second filter signal, and a frequency pass bandwidth of the second band pass filtering is narrower than a frequency pass bandwidth of the first band pass filtering.

Abstract: A method of operating a host device to control a storage device which includes a register is provided. The method includes: providing the storage device with a partial array refresh setting indicating a non-masking segment among a masking segment and the non-masking segment; providing a refresh command to the storage device; and providing a write command for the masking segment to the storage device to control the storage device to store data while a partial array refresh is performed in the storage device based on the refresh command.

Abstract: A hybrid communication device, an operation method thereof, and a communication system including the same are provided. The hybrid communication device includes a contact unit that includes an antenna for receiving a first communication signal and an electrode for receiving a second signal, a switch controller that includes a first switch and a second switch and controls the first switch and the second switch based on a change in capacitance of the electrode, and a signal processing unit that receives at least one of the first communication signal and the second communication signal from the contact unit via the first switch and processes the received signal. The first switch is connected to the contact unit, and the signal processing unit is connected to the first switch.

Abstract: A chain guide that contacts a chain connecting a cam sprocket and a crank sprocket, and has a contact portion contacting the back of the chain in a length direction of the chain and a convex curved line in a cross-section of the contact portion.

Abstract: The present invention relates to a method for optimizing power/ground pads in a power/ground distribution network. A power/ground distribution network is created for each of multiple voltage domains and a load current source of each node of the power/ground distribution network is modeled in consideration of the actual shapes and areas of functional blocks. A local optimization method is developed to solve problems generated when a conventional optimization method is applied to optimization of power/ground pads in a bump shape used for a flip chip, and a combination of global optimization and local optimization is applied to layouts using bump bonding, which is discriminated from the conventional optimization method restrictively applicable to layouts using wire bonding.

Abstract: Friction reducing units are integrally configured in a tensioner arm and a chain guide that are disposed at both sides of a timing chain to make contact with the timing chain, respectively to increase the thickness of the oil film, such that it is possible to improve durability of an entire timing chain system while preventing noise from being generated by reducing a friction loss generated on each of contact surfaces of the tensioner arm and the chain guide and prevent fuel efficiency of the vehicle from being deteriorated.

Abstract: A chain guide that contacts a chain connecting a cam sprocket and a crank sprocket, and has a contact portion contacting the back of the chain in a length direction of the chain and a convex curved line in a cross-section of the contact portion.

Abstract: The present invention relates to a method for optimizing power/ground pads in a power/ground distribution network. A power/ground distribution network is created for each of multiple voltage domains and a load current source of each node of the power/ground distribution network is modeled in consideration of the actual shapes and areas of functional blocks. A local optimization method is developed to solve problems generated when a conventional optimization method is applied to optimization of power/ground pads in a bump shape used for a flip chip, and a combination of global optimization and local optimization is applied to layouts using bump bonding, which is discriminated from the conventional optimization method restrictively applicable to layouts using wire bonding.

Abstract: The present invention relates to a method for designing initial placement of functional blocks and designing power distribution network of a semiconductor integrated circuit in the next stage of architecture level design of integrated circuit, which estimates the area and the quantity of power consumption of functional blocks and integrated circuit using design specifications of the functional blocks constructing the integrated circuit, that is, interconnection between functional blocks and an estimated size of the functional blocks which is determined in an architecture level design process. The present invention enables initial functional block placement in consideration of power consumption of the functional blocks and analyze reliability of power distribution network even prior to detailed circuit design.