Abstract: A memory device, and a method of operating the memory device, includes a memory block in which a plurality of cell pages are coupled to each of word lines. The memory device also includes a peripheral circuit configured to adjust a time point at which a verify voltage is applied to a selected word line among the word lines according to an order of performing a program operation during a verify operation of a selected cell page. The memory device further includes a control logic circuit configured to transmit, to the peripheral circuit, an operation code for adjusting a time point at which the verify voltage is output.

Abstract: A memory device may include: a control circuit suitable for performing a program loop including a program operation including a program voltage application operation on a selected word line and a bit line setup operation on a plurality of bit lines and a verification operation of applying (N?1) first verification voltages to the selected word line according to a predetermined order to check N types of first program states for each of a plurality of memory cells included in the selected word line; and control logic suitable for controlling the control circuit to repeatedly perform the program loop until programming for the selected word line is completed, and controlling the control circuit to apply any one of N types of column voltages to each of the plurality of bit lines in the bit line setup operation included in a second program loop.

Abstract: A method of managing identification information of a drone may include: generating an access message, wherein the access message includes an identifier for the ground identification device, which is a transmitter, an identifier for a receiver, an execution function command for classifying and defining a function to be performed, a serial number for transmitting information sequentially and retransmitting the information when transmission fails, data size information for informing a size of data to be transmitted, and transmission data; and transmitting the access message to an integrated management system corresponding to the identifier for the receiver.

Abstract: A memory device having an improved operation speed may include a memory block including memory cells, a peripheral circuit configured to perform a program operation of increasing each of threshold voltages of the memory cells, and a control logic configured to control the peripheral circuit to perform the program operation. The program operation may include a plurality of program loops, each of the plurality of program loops may include a program voltage apply operation and a verify operation, and the control logic may control the peripheral circuit to perform verification on a highest program state during a verify operation included in a next program loop of any one program loop, when verification of a next higher program state among the plurality of program states is passed during a verify operation included in the any one program loop among the plurality of program loops.

Abstract: A method and an apparatus for STR in a wireless LAN that supports multi-links are disclosed. An operating method of a first communication node comprises the steps of: transmitting a first frame to a second communication node through a first link from among multi-links; receiving, from the second communication node, a response frame for the first frame through the first link; checking a channel occupancy time in a second link from among the multi-links on the basis of first information included in the response frame; and performing a sensing operation in a preset section after the end of the channel occupancy time in the second link.

Abstract: An operation method performed by an apparatus for detecting multiple targets may comprise transmitting first signals using Mt transmit antennas included in the apparatus; receiving the first signals reflected by the multiple targets through Mr receive antennas included in the apparatus; generating a first function for estimating a velocity and an azimuth of each of the multiple targets using the first signals and the reflected first signals; estimating a velocity and an azimuth that maximize a result of the first function as a velocity and an azimuth of a first target closest to the apparatus among the multiple targets; generating a second function by cancelling interference caused by the first target from the first function; and estimating a velocity and an azimuth that maximize a result of the second function as a velocity and an azimuth of a second target among the multiple targets.

Abstract: Disclosed is a method for operating a communication node supporting a low power mode in a wireless LAN. A method for operating a station, which includes a PCR and a WURx, comprises the steps of: allowing the WURx, which operates in a wake-up state, to receive a wake-up packet from an access point; transitioning an operating state of the PCR from a sleep state to the wake-up state when the wake-up packet is received; allowing the PCR, which operates in the wake-up state, to receive a data frame from an access point; and allowing the PCR to transmit, to the access point, a response to the data frame.

Abstract: Provided herein may be a memory device capable of completing a foggy-fine program operation in one ready/busy period. The memory device may include a plurality of memory cells configured to form a plurality of pages, a peripheral circuit configured to perform a first program operation on a page adjacent to a selected page among the plurality of pages, and perform a second program operation on the selected page and control logic configured to control the peripheral circuit, during the first program operation, to successively receive least significant bit (LSB) page data, center significant bit (CSB) page data, and most significant bit (MSB) page data from a memory controller, and program the LSB page data to the page adjacent to the selected page and during the second program operation, to program the LSB page data programmed to the page adjacent to the selected page, the CSB page data and the MSB page data to the selected page.

Abstract: An operating method of a memory device, comprises: a program operation of applying a program voltage to a selected word line to program selected memory cells connected to the selected word line, a first verification operation of applying a first verification voltage to the selected word line and applying a first verification pass voltage to unselected word lines to verify a first program state of the selected memory cells, and a second verification operation of applying a second verification voltage to the selected word line and applying a second verification pass voltage to the unselected word lines to verify a second program state higher than the first program state.

Abstract: A method for sharing a multilink in a next-generation wireless LAN is disclosed. An operation method of a first communication node comprises the steps of: setting a transmission interval; communicating with a second communication node by using a first link and a second link in the transmission interval; sharing the transmission interval with a third communication node; and communicating with the second communication node by using the first link in the transmission interval.

Abstract: A memory system includes: a nonvolatile memory device including a plurality of memory blocks each including a plurality of memory cells coupled to a plurality of word lines; and a controller configured to control the nonvolatile memory device to perform a read operation on the plurality of memory blocks, wherein the read operation includes: a first operation of supplying a first voltage level to the plurality of word lines, a second operation of discharging the plurality of word lines to a second voltage level, a third operation of supplying a third voltage level less than the first voltage level to the plurality of word lines, and a fourth operation of discharging the plurality of word lines to a fourth voltage level.

Abstract: A memory device includes a first sub-block including word lines, a second sub-block including word lines, and a peripheral circuit configured to apply voltages to the word lines of the first sub-block and the word lines of the second sub-block. The memory device also includes control logic configured to control the peripheral circuit to perform a partial program operation of storing data in the first sub-block, when a plurality of memory cells included in the first sub-block are erased and a plurality of memory cells included in the second sub-block are programmed. The control logic includes a program operation controller for controlling the peripheral circuit to apply a verify operation to a selected word line of the word lines of the first sub-block and then apply a voltage having a constant level to the word lines of the second sub-block in the partial program operation.

Abstract: A memory device includes a cell group including a plurality of non-volatile memory cells capable of storing data and a control circuit configured to perform plural program loops for storing the data, each program loop including a program voltage application operation and a verification operation. During the respective program loop, the control circuit performs the verification operation for an N target level, an N?1 target level lower than the N target level, and an N+1 higher than the N target level, in response to the program voltage application operation for the N target level. When a quantity of non-volatile memory cells having threshold voltages over the N+1 target level satisfies a preset criterion, the control circuit skips a next verification for a target level lower than the N+1 target level, in response to a next program voltage application operation for the N+1 target level.

Abstract: The present disclosure relates to a memory device that includes a plurality of memory cells. The memory device also includes a peripheral circuit configured to perform a program operation of storing data in the plurality of memory cells, which includes a plurality of program loops each including an operation of applying a program voltage to a selected word line commonly connected to the plurality of memory cells and a verify operation of applying at least one verify voltage among verify voltages respectively corresponding to target program states of the plurality of memory cells. The memory device additionally includes control logic configured to control the peripheral circuit so that the at least one verify voltage increases according to a program loop of the plurality of program loops during the program operation.

Abstract: The present invention relates to a method for operating a first communication node in a wireless local area network (WLAN) supporting a multi-link operation, comprising the steps of: setting a first transmit window size of a first link for transmitting a plurality of frames to a second communication node; transmitting the plurality of frames through the first link; when the state of a channel detected through channel sensing in the second link is an idle state, setting a transmit opportunity (TXOP) in the channel; and when the transmit opportunity is set, performing an agreement with the second communication node on the size of a second transmit window for transmitting the plurality of frames. Therefore, it is possible to improve the performance of a communication system.

Abstract: The present invention relates to an operating method of a first communication node in a communication system, comprising the steps of: negotiating with a second communication node with respect to a parameter for multi-link transmission; determining, on the basis of the parameter, a plurality of links for performing the multi-link transmission, and the transmission method by which the multi-link transmission is performed; and transmitting, in the plurality of links, a data frame to the second communication node by means of the transmission method. Therefore, the communication node can efficiently set and change links.

Abstract: Apparatuses, systems, and techniques to perform effective tone management for image data. In an embodiment, a set of contrast gain curves are generated corresponding to a set of tonal ranges of an input image. An output image may then be generated by at least applying corresponding contrast gain curves to tonal ranges of the input image.

Abstract: A memory device having an improved operation speed includes: a memory cell; a page buffer circuit connected to the memory cell through a bit line; and a program operation controller for controlling an operation of the page buffer circuit. The page buffer circuit includes: a bit line voltage supply for providing a precharge voltage to the bit line; a sensing node voltage supply for providing a sensing node precharge voltage to a sensing node connected to the bit line; a first latch for storing first verify data; a sensing node connector for releasing connection between the bit line and the sensing node, after the first verify data is stored; and a second latch for storing second verify data determined according to the voltage of the sensing node, after the connection between the bit line and the sensing node is released.

Abstract: The present technology relates to an electronic device. According to the present technology, a method of operating a memory device including a program operation speed in which an effect of a disturbance is reduced, and including a plurality of memory blocks each including a plurality of memory cell strings each including a plurality of memory cells connected in series between a bit line and a source line, a plurality of source select transistors connected in series between the source line and the plurality of memory cells, and a plurality of drain select transistors connected in series between the bit line and the plurality of memory cells, includes applying a precharge voltage to the source line, and applying the precharge voltage to a first source select line connected to a source select transistor adjacent to the source line among source select transistors included in an unselected memory block among the plurality of memory blocks.

Abstract: A memory device having an improved operation speed may include a memory block including memory cells, a peripheral circuit configured to perform a program operation of increasing each of threshold voltages of the memory cells, and a control logic configured to control the peripheral circuit to perform the program operation. The program operation may include a plurality of program loops, each of the plurality of program loops may include a program voltage apply operation and a verify operation, and the control logic may control the peripheral circuit to perform verification on a highest program state during a verify operation included in a next program loop of any one program loop, when verification of a next higher program state among the plurality of program states is passed during a verify operation included in the any one program loop among the plurality of program loops.