Patents by Inventor Sung-Hyun Kwon

Sung-Hyun Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978911
    Abstract: The present invention relates to a three-dimensional structure electrode, a method for manufacturing same, and an electrochemical element including the electrode. The present invention is characterized by comprising: (a) an upper conductive layer and a lower conductive layer which have a structure constituting an assembly within which a conductive material and a porous nonwoven fabric including a plurality of polymeric fibers are three-dimensionally connected in an irregular and continuous manner, thereby forming a mutually connected porous structure; and (b) an active material layer forming the same assembly structure as the conductive layers and forming a three-dimensionally filled structure in which electrode active material particles are uniformly filled inside the mutually connected porous structure formed in the assembly structure, wherein the active material layer is formed between the upper conductive layer and the lower conductive layer.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: May 7, 2024
    Assignees: UNIST (Ulsan National Institute of Science and Technology), LG Energy Solution, Ltd.
    Inventors: In Sung Uhm, Sang Young Lee, Yo Han Kwon, Ju Myung Kim, Joon Won Lim, Jae Hyun Lee, Je Young Kim, Seong Hyeok Kim
  • Publication number: 20240096557
    Abstract: A capacitor component includes a body having a first surface and a second surface opposing each other and including a multilayer structure in which a plurality of dielectric layers are stacked and first and second internal electrodes are alternately disposed with respective dielectric layers interposed therebetween and exposed to the first surface and the second surface, respectively, first and second metal layers covering the first surface and the second surface and connected to the first and second internal electrodes, respectively, first and second ceramic layers covering the first and second metal layers, and first and second external electrodes covering the first and second ceramic layers and connected to the first and second metal layers to be electrically connected to the first and second internal electrodes, respectively.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Inventors: Sung Hyun CHO, Byeong Chan KWON, Yong Jin YUN, Ki Pyo HONG, Jae Yeol CHOI
  • Publication number: 20240074708
    Abstract: It is disclosed a blood glucose prediction system and method using saliva-based artificial intelligence deep learning technique.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Applicant: DONG WOON ANATECH CO., LTD.
    Inventors: In Su Jang, Min Su Kwon, Hee Jung Kwon, Sung Hwan Chung, Eun Hye Im, Ji Won Kye, Eun Hyun Shim, Hee Jin Kim, Mi Rim Kim, Hyun Seok Cho, Dong Cheol Kim
  • Patent number: 11924790
    Abstract: Provided is a method and apparatus for receiving a reference signal. A wireless user device may determine, based on a synchronization signal (SS) block index and based on an index associated with a time interval, an initialization value associated with a reference signal for a physical broadcast channel (PBCH). The wireless user device may receive, based on the initialization value and based on a frequency domain shift value, the reference signal via at least one resource element (RE). The reference signal may be mapped, based on the frequency domain shift value, to the at least one RE. The wireless user device may receive the PBCH.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: March 5, 2024
    Assignee: Innovative Technology Lab Co., Ltd.
    Inventors: Dong Hyun Park, Sung Jun Yoon, Ki Bum Kwon
  • Publication number: 20240072712
    Abstract: Provided an electronic device including a main body and a kit connected to the main body, and the main body includes a battery, a first motor, an electric wire connected to the battery, and a first controller connected to the electric wire, the kit includes a second motor supplied with power through the electric wire, an inverter connected to the second motor, and a second controller connected to the electric wire and configured to control driving of the inverter, and the second controller is configured to transmit information to the first controller through switching frequency control of the inverter and control a switching frequency of the inverter so that a current associated with the second motor is greater than zero in a section in which transmission of the information is performed.
    Type: Application
    Filed: March 9, 2021
    Publication date: February 29, 2024
    Inventors: Se Hwa CHOE, Cha Seung JUN, Sung Yong SHIN, Sun Ku KWON, Dong Hyun LIM
  • Publication number: 20240069535
    Abstract: The present disclosure relates to a simulation apparatus for secondary battery production.
    Type: Application
    Filed: July 14, 2022
    Publication date: February 29, 2024
    Inventors: Shinkyu KANG, Min Yong KIM, Youngduk KIM, Nam Hyuck KIM, Su Ho JEON, Min Hee KWON, Sung Nam CHO, Hyeong Geun CHAE, Gyeong Yun JO, Moon Kyu JO, Kyungchul HWANG, Moo Hyun YOO, Han Seung KIM, Daewoon JUNG, Seungtae KIM, Junhyeok JEON
  • Patent number: 11914145
    Abstract: Disclosed in the present invention is a floating hologram system. The floating hologram system includes a diffuser configured to form a projection image using light beams transmitted from an image transmitter and diffuse the formed image, and a holographic optical element on which the image diffused from the diffuser is incident and which generates a virtual image floating at a position a predetermined distance therefrom and has a convex lens characteristic. A distance between the diffuser and the holographic optical element is determined based on a focal length of the holographic optical element and a distance from the holographic optical element to the virtual image.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: February 27, 2024
    Assignee: KWANGWOON UNIVERSITY INDUSTRY-ACADEMIC COLLABORATION FOUNDATION
    Inventors: Seung Hyun Lee, Lee Hwan Hwang, Jae Hyun Lee, Sung Jae Ha, Soon Chul Kwon, Kwang Pyo Hong
  • Patent number: 11396042
    Abstract: A serial multi-cavity high pressure casting apparatus includes a three stage mold comprising a fixed mold, an operation mold, and a medium mold disposed between the fixed mold and the operation mold, a main sleeve penetrating a lower portion of the fixed mold, and having molten metal injected thereinto, a main runner formed to extend upward from the main sleeve, an auxiliary sleeve branched to both directions from the main runner, an auxiliary runner formed to extend upward from each of both ends of the auxiliary sleeve and connected to each of a first cavity formed between the fixed mold and the medium mold, and a second cavity formed between the medium mold and the operation mold, and a sleeve core disposed on a lower portion of the medium mold, and having the main sleeve, the main runner, and the auxiliary sleeve inserted thereinto.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: July 26, 2022
    Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATION
    Inventors: Cheol-Ung Lee, Ji-Yong Lee, Dae-Ho Lee, Seong-Jun Lim, Hyo-Moon Joo, Cheon-Hee Kim, Sung-Hyun Kwon, Yoon-Ki Lee
  • Patent number: 7772069
    Abstract: A method of forming a semiconductor device is provided. A plurality of first guide patterns are formed on a substrate. A mask layer is conformally formed on the substrate. Second guide patterns are formed in empty regions on respective sides of the first guide patterns. The mask layer is planarized and the first and second guide patterns are removed. The mask layer is etched by an anisotropic etching process.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: August 10, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Yong Park, Sung-Hyun Kwon, Jae-Hwang Sim, Keon-Soo Kim, Jae-Kwan Park
  • Patent number: 7521348
    Abstract: A method for fabricating a semiconductor device having fine contact holes is exemplarily disclosed. The method includes forming an isolation layer defining active regions on a semiconductor substrate. An interlayer dielectric layer is formed on the semiconductor substrate having the isolation layer. First molding patterns are formed on the interlayer dielectric layer. Second molding patterns positioned between the first molding patterns and spaced apart therefrom are also formed. A mask pattern surrounding sidewalls of the first and second molding patterns is formed. Openings are formed by removing the first and second molding patterns. Contact holes are formed by etching the interlayer dielectric layer using the mask pattern as an etching mask.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: April 21, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hyun Kwon, Jae-Hwang Sim, Dong-Hwa Kwak, Joo-Young Kim
  • Publication number: 20080227258
    Abstract: Methods of forming a semiconductor device include forming a mask layer on a semiconductor substrate. The mask layer has vertically and horizontally extending portions. The vertically extending portions have a thickness selected to provide a desired line width to an underlying structure to be formed using the mask layer and a height greater than a height of the horizontally extending portions. The underlying structure is formed using the mask layer.
    Type: Application
    Filed: March 7, 2008
    Publication date: September 18, 2008
    Inventors: Sang-Yong Park, Sung-Hyun Kwon, Jae-Hwang Sim, Keon-Soo Kim, Jae-Kwan Park
  • Publication number: 20080096391
    Abstract: A method for fabricating a semiconductor device having fine contact holes is exemplary disclosed. The method includes forming an isolation layer defining active regions on a semiconductor substrate. An interlayer dielectric layer is formed on the semiconductor substrate having the isolation layer. First molding patterns are formed on the interlayer dielectric layer. Second molding patterns positioned between the first molding patterns and spaced apart therefrom are also formed. A mask pattern surrounding sidewalls of the first and second molding patterns is formed. Openings are formed by removing the first and second molding patterns. Contact holes are formed by etching the interlayer dielectric layer using the mask pattern as an etching mask.
    Type: Application
    Filed: October 12, 2007
    Publication date: April 24, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Hyun KWON, Jae-Hwang SIM, Dong-Hwa KWAK, Joo-Young KIM