Abstract: In one embodiment, the memory device includes at least one memory bank including first and second subbanks, and control logic configured to control storing data into the memory bank. The control logic is configured to activate the first subbank and to precharge the second subbank in response to a first activate command for the first subbank.

Abstract: A system on chip (SOC) includes a slave device, a plurality of master devices, an interconnect device and a plurality of service controllers. The master devices generate requests to demand services from the slave device. The interconnect device is coupled to the slave device and the master devices through respective channels, and the interconnect device performs an arbitrating operation on the requests. The service controllers control request flows from the master devices adaptively depending on an operational environment change of the SOC.

Abstract: In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module.

Abstract: A method of managing dynamic memory reallocation includes receiving an input address including a block bit part, a tag part, and an index part and communicating the index part to a tag memory array, receiving a tag group communicated by the tag memory array based on the index part, analyzing the tag group based on the block bit part and the tag part and changing the block bit part and the tag part based on a result of the analysis, and outputting an output address including a changed block bit part, a changed tag part, and the index part.

Abstract: An method of operating a data cache controller is provided. The method includes transmitting first data output from a data cache to a central processing unit (CPU) core with a first latency and transmitting second data to the CPU core with a second latency greater than the first latency. The first latency is a delay between a read request to the data cache and transmission of the first data according to execution of a first instruction fetched from an instruction cache, and the second latency is a delay between a read request to the data cache and transmission of the second data according to execution of a second instruction fetched from the instruction cache.

Abstract: The present invention relates to a light-emitting diode chip. According to the present invention, the light-emitting diode chip comprises: a substrate, the thickness of which is greater than 120 ?m; and a light-emitting diode provided on the surface of the substrate, at one side thereof.

Abstract: An method of operating a data cache controller is provided. The method includes transmitting first data output from a data cache to a central processing unit (CPU) core with a first latency and transmitting second data to the CPU core with a second latency greater than the first latency. The first latency is a delay between a read request to the data cache and transmission of the first data according to execution of a first instruction fetched from an instruction cache, and the second latency is a delay between a read request to the data cache and transmission of the second data according to execution of a second instruction fetched from the instruction cache.

Abstract: Disclosed herein are a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes: a substrate, a light-emitting layer disposed on a surface of the substrate and including a first type semiconductor layer, an active layer, and a second type semiconductor layer, a first bump disposed on the first type semiconductor layer and a second bump disposed the second type semiconductor layer, a protective layer covering at least the light-emitting layer, and a first bump pad and a second bump pad disposed on the protective layer and connected to the first bump and the second bump, respectively.

Abstract: In a semiconductor memory device and an internal data transmission method thereof, the device includes a memory controller, a pair of data lines, and a plurality of memory banks. During an internal data transmission operation, the memory controller externally receives and stores a source address and a target address in response to an externally applied command and outputs an internal control signal and an internal address signal using the source address and the target address. The internal control signal includes an internal write signal and an internal read signal. Transmission data is transmitted on the pair of data lines during the internal data transmission operation. The plurality of memory banks read the transmission data stored in a region corresponding to the source address in response to the internal read signal, transmit the transmission data on the pair of data lines, and write the transmission data transmitted on the pair of data lines in response to the internal write signal.

Abstract: In a semiconductor memory device and an internal data transmission method thereof, the device includes a memory controller, a pair of data lines, and a plurality of memory banks. During an internal data transmission operation, the memory controller externally receives and stores a source address and a target address in response to an externally applied command and outputs an internal control signal and an internal address signal using the source address and the target address. The internal control signal includes an internal write signal and an internal read signal. Transmission data is transmitted on the pair of data lines during the internal data transmission operation. The plurality of memory banks read the transmission data stored in a region corresponding to the source address in response to the internal read signal, transmit the transmission data on the pair of data lines, and write the transmission data transmitted on the pair of data lines in response to the internal write signal.

Abstract: A memory system comprises a processor, a main memory comprising a volatile random access memory (RAM) that stores data to be accessed by the processor and a nonvolatile memory that provides a swap space for the RAM, and a disk that provides data transfer to the RAM with a greater latency than the nonvolatile memory.

Abstract: The invention relates to a bait reel for fishing including: a handle; a spool, the spool being adapted to wind a fishing line and to unwind the fishing line by a reverse rotation; and a brake device which includes: a one-way clutch bearing coupled to a rotary shaft of the spool and constrained in the rotation upon the reverse rotation of the spool; a brake disc on which the one-way clutch bearing is fixed, the brake disc is rotated integrally together with the one-way clutch bearing upon the reverse rotation of the spool; and a manipulating member having a brake shoe fixedly mounted at one end portion and hinge-coupled to a casing to which the spool is fixed such that rotation is allowed by an angle to permit the brake shoe to come into close contact with the brake disc, thereby allowing a braking force to be adjustable.

Abstract: An apparatus and method for driving a plasma display panel wherein an initializing discharge can be weakened to lower a dark room brightness and an initialization time can be shortened to permit a single scanning. In the apparatus, a sensing device senses an electrical signal with an initialization waveform applied from a voltage source to a display panel. A controlling device controls said electrical signal with an initialization waveform applied from the voltage source to the display panel by the sensed electrical signal.

Abstract: An optical power splitter is provided that can stably operate even when there is a mode mismatch between an input optical signal and the optical power splitter. The optical power splitter of the present invention includes a semiconductor substrate, an optical waveguide stacked on the semiconductor substrate, and a clad surrounding the optical waveguide.

Abstract: A plasma display panel driving method that is adaptive for improving contrast. In the method, at least one of the first and second electrodes keeps a floating state in an initialization period of at least one sub-field of a plurality of sub-fields.

Abstract: An optical power splitter is provided that can stably operate even when there is a mode mismatch between an input optical signal and the optical power splitter. The optical power splitter of the present invention includes a semiconductor substrate, an optical waveguide stacked on the semiconductor substrate, and a clad surrounding the optical waveguide.

Abstract: A plasma display panel driving method that is adaptive for improving contrast. In the method, at least one of the first and second electrodes keeps a floating state in an initialization period of at least one sub-field of a plurality of sub-fields.

Abstract: A planar light waveguide circuit includes a plurality of landmarks arranged on the planar light waveguide circuit at intervals of a specific gap starting from a cut section of the planar light waveguide circuit so as to increase the uniformity of a coupling loss that occurs when connecting the planar light waveguide circuit in alignment with optical fiber blocks, wherein the landmarks are formed onto the planar light waveguide circuit so as to enable an operator to monitor a permissible angle error, and wherein Arabic numerals or specific symbols are marked in association with the landmarks to help the operator distinguish the landmarks.

Abstract: An apparatus and method for driving a plasma display panel wherein an initializing discharge can be weakened to lower a dark room brightness and an initialization time can be shortened to permit a single scanning. In the apparatus, a sensing device senses an electrical signal with an initialization waveform applied from a voltage source to a display panel. A controlling device controls said electrical signal with an initialization waveform applied from the voltage source to the display panel by the sensed electrical signal.

Abstract: A planar light waveguide circuit includes a plurality of landmarks arranged on the planar light waveguide circuit at intervals of a specific gap starting from a cut section of the planar light waveguide circuit so as to increase the uniformity of a coupling loss that occurs when connecting the planar light waveguide circuit in alignment with optical fiber blocks, wherein the landmarks are formed onto the planar light waveguide circuit so as to enable an operator to monitor a permissible angle error, and wherein Arabic numerals or specific symbols are marked in association with the landmarks to help the operator distinguish the landmarks.