Patents by Inventor Sung Hyun Oh

Sung Hyun Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250054948
    Abstract: A cathode active material with controlled rheological properties for lithium secondary batteries. In particular, the cathode active material for a lithium secondary battery includes: a core part comprising a lithium metal oxide; and a coating layer covering at least a portion of a surface of the core part and comprising an inorganic compound.
    Type: Application
    Filed: December 5, 2023
    Publication date: February 13, 2025
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, WONIK QnC CORPORATION
    Inventors: Je Sik Park, Hong Seok Min, Sung Woo Noh, Jeong Hyun Seo, Im Sul Seo, Ju Yeong Seong, Chung Bum Lim, Hyuk Chun Kwon, Ho Chang Lee, Seong Uk Oh, Ji Su Kim, Jong Hyun Park
  • Publication number: 20250055006
    Abstract: A reinforced composite membrane with improved ion conductivity and wettability is provided. Provided in one embodiment of the present disclosure is a reinforced composite membrane comprising a porous support and an ionomer layer, which comprises an ion conductor filling the pores inside the porous support, wherein the porous support comprises a first surface and a second surface opposite to the first surface, and the first surface is reformed to contain a first hydrophilic functional group.
    Type: Application
    Filed: November 23, 2022
    Publication date: February 13, 2025
    Inventors: Jung Hwa PARK, Dong Hoon LEE, Kum Suck SONG, Sung Hyun YUN, Seung Jib YUM, Chang Hoon OH, Hye Song LEE, Eun Su LEE
  • Patent number: 12223844
    Abstract: A method of managing identification information of a drone may include: generating an access message, wherein the access message includes an identifier for the ground identification device, which is a transmitter, an identifier for a receiver, an execution function command for classifying and defining a function to be performed, a serial number for transmitting information sequentially and retransmitting the information when transmission fails, data size information for informing a size of data to be transmitted, and transmission data; and transmitting the access message to an integrated management system corresponding to the identifier for the receiver.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: February 11, 2025
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Su Na Choi, Kyu Min Kang, Jae Cheol Park, Jin Hyung Oh, Dong Woo Lim, Sung Hyun Hwang
  • Publication number: 20250048404
    Abstract: A D2D scheduling method in a UAV-based IoT network includes: (a) acquiring a geographical map for all transmission links of a D2D network within a network coverage area; (b) applying the geographical map to a sparse convolution model to extract a feature map; (c) defining the feature map for a time slot t as a state St, and then inputting the feature map to actor and critic networks of a reinforcement learning-based scheduling policy learning model, respectively, and selecting a scheduling decision At for the D2D transmission link based on a scheduling output of the actor network and a greedy strategy; and (d) transmitting the scheduling decision At to the D2D network and then receiving reward when the scheduling decision At is applied by the D2D network, wherein the reward is calculated as a total achievable transmission rate.
    Type: Application
    Filed: June 11, 2024
    Publication date: February 6, 2025
    Inventors: Sung Rae CHO, Jun Suk OH, Dong Hyun LEE, Van Dat TUONG
  • Publication number: 20250038732
    Abstract: The present invention provides a surface acoustic wave filter with a mass addition film formed on a plurality of electrodes. The surface acoustic wave filter includes a substrate on which a support substrate, an energy confinement layer, and a piezoelectric layer are sequentially stacked; first and second bus bars extended in a first direction on the substrate and spaced apart from each other in a second direction perpendicular to the first direction; a plurality of IDT electrodes alternately extended from the first and second bus bars in the second direction and spaced apart from each other in the first direction; and a mass addition film extended in the first direction to cover the top surface of the plurality of IDT electrodes and the top surface of the substrate exposed between the plurality of IDT electrodes.
    Type: Application
    Filed: July 21, 2024
    Publication date: January 30, 2025
    Inventors: Hun Yong LEE, Hae Kwan OH, Sung Hyun LEE
  • Patent number: 8802335
    Abstract: An extreme ultra violet (EUV) mask is disclosed, which prevents defects from shot overlap encountered in wafer exposure as well as reflection of unnecessary EUV and DUV generated in a black border region, such that a pattern CD is reduced and defects are not created. The EUV mask includes a quartz substrate, a multi-layered reflection film formed over the quartz substrate to reflect exposure light, an absorption layer formed over the multi-layered reflection film, a black border region formed over the quartz substrate that does not include the multi-layered reflection film, and a blind layer formed in a position including at least one of over the absorption layer, over the quartz substrate, and below the quartz substrate.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: August 12, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sung Hyun Oh, Yoon Suk Hyun
  • Publication number: 20120135340
    Abstract: A method for forming a photomask includes detecting a defect of the photomask which has a mirror layer formed on a first surface of a substrate, and forming a recess groove on a first layer which is formed on a second surface of the substrate, wherein the coordinate of the recess groove corresponds to the coordinate of the defect.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 31, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Sung Hyun OH
  • Patent number: 8163445
    Abstract: An EUV mask comprises a multi-reflecting layer is formed over a substrate and reflecting EUV light; an absorber layer pattern defining a sidewall formed over the multi-reflecting layer formed and selectively exposing a region of the multi-reflecting layer; and a reflecting spacer which additionally reflects the EUV light at the sidewall of the absorber layer pattern.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: April 24, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Hyun Oh
  • Patent number: 8158305
    Abstract: A method for fabricating a photomask for extreme ultraviolet lithography is provided. A reflection layer reflecting extreme ultraviolet light is formed over a transparent substrate having a main chip region and a frame region. A phase shifter pattern is formed over the reflection layer to selectively expose the reflection layer. An absorber pattern is formed over the phase shifter pattern of the frame region. A reflectivity reduction region guiding the shielding of the extreme ultraviolet light is formed in the absorber pattern.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: April 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Hyun Oh
  • Publication number: 20110250528
    Abstract: A method for correcting an image placement error in a photomask includes, forming a photomask including a light absorbing layer formed on a frame region of a substrate and a mask pattern formed on a field region inside the frame region, measuring a first registration error of the photomask, and etching a portion of the light absorbing layer on the frame region to induce a second registration error for compensating the first registration error.
    Type: Application
    Filed: April 11, 2011
    Publication date: October 13, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Sung Hyun OH
  • Patent number: 8021805
    Abstract: A mask includes mask patterns formed over a frontside of a substrate and a phase grating formed over a backside of the substrate. The mask patterns correspond to a layout of diagonal patterns extending in a direction rotated toward a predetermined direction from an axis of a rectangular coordinate system. The phase grating extends in a direction parallel to the extending direction of the mask patterns. The phase grating includes first and second phase regions alternately arranged over the backside of the substrate with a phase difference of 180° therebetween. The first and second phase regions induce a phase interference that blocks a zero-order light of an exposure light incident to the substrate and allows a primary light to be incident to the mask patterns.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: September 20, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Hyun Oh, Byung Ho Nam
  • Patent number: 7977016
    Abstract: A method for fabricating an extreme ultraviolet (EUV) lithography mask comprises forming a reflecting layer, an absorber layer, and a resist layer over a substrate; defining a plurality of split regions by partially splitting the resist layer with regular spacing; performing an exposure process, wherein the exposure region is irradiated with an electron beam at different intensities on the split regions to generate a difference in electron beam doses implanted into the resist layer; forming a resist layer pattern which selectively exposes the absorber layer and has a slanted side wall profile by performing a development process to remove a portion of the resist layer, into which the electron beam doses are implanted; and forming an absorber layer pattern with a slanted side wall profile by sequentially etching the portion of the absorber layer exposed by the resist layer pattern.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: July 12, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Hyun Oh, Yong Kyoo Choi
  • Publication number: 20100304277
    Abstract: A method for fabricating a photomask for extreme ultraviolet lithography is provided. A reflection layer reflecting extreme ultraviolet light is formed over a transparent substrate having a main chip region and a frame region. A phase shifter pattern is formed over the reflection layer to selectively expose the reflection layer. An absorber pattern is formed over the phase shifter pattern of the frame region. A reflectivity reduction region guiding the shielding of the extreme ultraviolet light is formed in the absorber pattern.
    Type: Application
    Filed: December 30, 2009
    Publication date: December 2, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Sung Hyun Oh
  • Patent number: 7803505
    Abstract: In a method of fabricating a mask for a semiconductor device, a phase shift layer and a light blocking layer are formed on a transparent substrate. The light blocking layer is patterned to form light blocking patterns which partially expose a surface of the phase shift layer. An extension defect or a bridge defect is detected. A photoresist layer, which does not react to light, is formed on a resulting structure including the detected defect. The extension defect is removed by performing a repair process on the light blocking patterns. The bridge defect is removed by etching using the light blocking patterns as a mask.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: September 28, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Hyun Oh
  • Patent number: 7764368
    Abstract: Provided are a method and apparatus for inspecting mask defects. The method may include preparing a mask with a defect inspecting pattern, formed on a transparent substrate. The method may further include preparing a wafer defect inspecting apparatus including a defect inspecting unit capable of detecting defects through radiating light on a surface of a mask and obtaining an image based on reflected light, and a mask stage on which the mask is mounted facing the defect inspecting unit. The mask stage may replace the wafer stage of a wafer defect inspecting apparatus, and the mask stage may support the mask at a surface height substantially equal to a surface height of the wafer mounted on the wafer stage. The method may also include mounting the mask on the mask stage and detecting mask defects through operating the defect inspecting unit to radiate light on a surface of the mask and obtain an image based on reflected light.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: July 27, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Hyun Oh, Yong Kyoo Choi, Byung Sup Cho
  • Publication number: 20100167182
    Abstract: A mask includes mask patterns formed over a frontside of a substrate and a phase grating formed over a backside of the substrate. The mask patterns correspond to a layout of diagonal patterns extending in a direction rotated toward a predetermined direction from an axis of a rectangular coordinate system. The phase grating extends in a direction parallel to the extending direction of the mask patterns. The phase grating includes first and second phase regions alternately arranged over the backside of the substrate with a phase difference of 180° therebetween. The first and second phase regions induce a phase interference that blocks a zero-order light of an exposure light incident to the substrate and allows a primary light to be incident to the mask patterns.
    Type: Application
    Filed: June 26, 2009
    Publication date: July 1, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventors: Sung Hyun OH, Byung Ho Nam
  • Publication number: 20090317728
    Abstract: A method for fabricating an extreme ultraviolet (EUV) lithography mask comprises forming a reflecting layer, an absorber layer, and a resist layer over a substrate; defining a plurality of split regions by partially splitting the resist layer with regular spacing; performing an exposure process, wherein the exposure region is irradiated with an electron beam at different intensities on the split regions to generate a difference in electron beam doses implanted into the resist layer; forming a resist layer pattern which selectively exposes the absorber layer and has a slanted side wall profile by performing a development process to remove a portion of the resist layer, into which the electron beam doses are implanted; and forming an absorber layer pattern with a slanted side wall profile by sequentially etching the portion of the absorber layer exposed by the resist layer pattern.
    Type: Application
    Filed: December 31, 2008
    Publication date: December 24, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Sung Hyun Oh, Yong Kyoo Choi
  • Publication number: 20090233185
    Abstract: An EUV mask comprises a multi-reflecting layer is formed over a substrate and reflecting EUV light; an absorber layer pattern defining a sidewall formed over the multi-reflecting layer formed and selectively exposing a region of the multi-reflecting layer; and a reflecting spacer which additionally reflects the EUV light at the sidewall of the absorber layer pattern.
    Type: Application
    Filed: December 30, 2008
    Publication date: September 17, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Sung Hyun Oh
  • Publication number: 20080280213
    Abstract: In a method of fabricating a mask for a semiconductor device, a phase shift layer and a light blocking layer are formed on a transparent substrate. The light blocking layer is patterned to form light blocking patterns which partially expose a surface of the phase shift layer. An extension defect or a bridge defect is detected. A photoresist layer, which does not react to light, is formed on a resulting structure including the detected defect. The extension defect is removed by performing a repair process on the light blocking patterns. The bridge defect is removed by etching using the light blocking patterns as a mask.
    Type: Application
    Filed: December 4, 2007
    Publication date: November 13, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventor: Sung Hyun OH
  • Publication number: 20080186497
    Abstract: Provided are a method and apparatus for inspecting mask defects. The method may include preparing a mask with a defect inspecting pattern, formed on a transparent substrate. The method may further include preparing a wafer defect inspecting apparatus including a defect inspecting unit capable of detecting defects through radiating light on a surface of a mask and obtaining an image based on reflected light, and a mask stage on which the mask is mounted facing the defect inspecting unit. The mask stage may replace the wafer stage of a wafer defect inspecting apparatus, and the mask stage may support the mask at a surface height substantially equal to a surface height of the wafer mounted on the wafer stage. The method may also include mounting the mask on the mask stage and detecting mask defects through operating the defect inspecting unit to radiate light on a surface of the mask and obtain an image based on reflected light.
    Type: Application
    Filed: December 27, 2007
    Publication date: August 7, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Sung Hyun Oh, Yong Kyoo Choi, Byung Sup Cho