Abstract: Disclosed is an interface system including a first neuron cluster that outputs a first neuron signal including a first neuron request and first neuron data by performing a first arithmetic operation, and a first interface circuit that stores the first neuron data and outputs a first response, in response to the first neuron request. The first neuron cluster outputs a second neuron signal including a second neuron request and second neuron data by performing a second arithmetic operation, in response to the first response. Before the first data is transmitted to a second neuron cluster different from the first neuron cluster, the first interface circuit outputs the first response in response to a fact that the first neuron data is stored.

Abstract: Disclosed are a fingerprint forgery detection device and a method of operating the same. The fingerprint forgery detection device includes a memory that stores a first feature signal including biological channel feature information of a user, a transmitter including at least one transmission electrode for transmitting a pulse signal to the user, a receiver including at least one reception electrode for receiving a biological channel response signal in response to the transmitted pulse signal, and a signal processor for processing the biological channel response signal to detect whether a fingerprint is forged, and at least one processor that controls the memory, the transmitter, and the receiver.

Abstract: Disclosed is an amplification circuit, which includes a first amplifier that receives an external signal and performs first band pass filtering on the external signal to output a first filter signal, and a second amplifier that receives the first filter signal and performs second band pass filtering on the first filter signal to output a second filter signal, and a frequency pass bandwidth of the second band pass filtering is narrower than a frequency pass bandwidth of the first band pass filtering.

Abstract: A hybrid communication device, an operation method thereof, and a communication system including the same are provided. The hybrid communication device includes a contact unit that includes an antenna for receiving a first communication signal and an electrode for receiving a second signal, a switch controller that includes a first switch and a second switch and controls the first switch and the second switch based on a change in capacitance of the electrode, and a signal processing unit that receives at least one of the first communication signal and the second communication signal from the contact unit via the first switch and processes the received signal. The first switch is connected to the contact unit, and the signal processing unit is connected to the first switch.

Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench and a post by etching an upper surface of a base substrate including a conductive material, filling the trench with a resin, removing the resin exposed to outside of the trench such that an upper surface of the post and an upper surface of the resin are at same level, forming a conductive layer on an entire area of the upper surface of the post and the upper surface of the resin, and forming a circuit wiring including an upper circuit wiring and a lower circuit wiring by simultaneously patterning the conductive layer and a lower surface of the base substrate.

Abstract: A method of manufacturing a circuit board includes preparing a substrate having electrical conductivity, removing a portion of a first surface of the substrate to form a plurality of pillars on the first surface of the substrate, locating an insulating material on the first surface of the substrate to cover a space between the plurality of pillars of the substrate, forming a pattern on a second surface, which is opposite to the first surface of the substrate, by removing a portion of the second surface of the substrate, forming a first metal layer on the first surface of the substrate, and forming a second metal layer on the second surface of the substrate.

Abstract: A lead frame includes: leads; and a dambar arranged between the leads and connecting the leads to each other, wherein each of the leads includes: a lower lead groove formed in a first surface for a wettable flank structure; and an upper lead groove formed in a second surface opposite the first surface and aligned with the lower lead groove in a thickness direction, wherein in a sawing process, a portion of the lead between the lower lead groove and the upper lead groove is at least partially removed.

Abstract: Provided are a semiconductor package substrate, a method of manufacturing the semiconductor package substrate, and a semiconductor package. According to one embodiment of the present disclosure, a semiconductor package substrate includes a base substrate having a lower surface in which a first trench is provided and an upper surface in which a second trench and a third trench are provided, including a circuit pattern and a conductive material; a first resin arranged in the first trench; and a second resin arranged in the second trench and the third trench, wherein the second trench exposes at least a part of the first resin.

Abstract: A semiconductor package substrate and a method of manufacturing the same are provided. The semiconductor package substrate includes: a base layer including a conductive material, having a first surface and a second surface opposite the first surface, and having a first groove or first trench in the first surface and a second groove or second trench in the second surface; a first resin buried in the first groove or first trench in the first surface of the base layer; and a groove in at least one corner of the first surface of the base layer and having a depth based on the first surface is 1/2 or more of a thickness of the base layer.

Abstract: A substrate surface grinding apparatus includes: a grinding device including a plurality of grinding rollers configured to grind a surface of a substrate; and a substrate support member configured to support the substrate, wherein rotational axes of the grinding rollers are disposed to be inclined to rotational axes of adjacent grinding rollers.

Abstract: According to an embodiment of the disclosure, a method of fabricating a carrier for a wafer level package (WLP) by using a lead frame, wherein the lead frame is fabricated by forming a trench and a post by performing first half etching on an upper surface of a base substrate comprising a conductive material, filling the first-half-etched surface with resin of an insulating material, removing the resin exposed to outside of the trench so that an upper surface of the trench and an upper surface of the resin are at a same level, and performing second half etching on a lower surface of the base substrate, in which a memory chip is attached to the lower surface of the base substrate.

Abstract: A method of manufacturing a circuit board includes preparing a substrate having electrical conductivity, removing a portion of a first surface of the substrate to form a plurality of pillars on the first surface of the substrate, locating an insulating material on the first surface of the substrate to cover a space between the plurality of pillars of the substrate, forming a pattern on a second surface, which is opposite to the first surface of the substrate, by removing a portion of the second surface of the substrate, forming a first metal layer on the first surface of the substrate, and forming a second metal layer on the second surface of the substrate.

Abstract: According to one or more embodiments, there is provided an apparatus for polishing a surface of a substrate to remove a resin layer formed on the surface of the substrate having a groove, the apparatus including: a laser irradiation apparatus configured to irradiate a laser to the resin layer to remove at least a portion of a resin from the resin layer except for a portion of the resin layer arranged in the groove.

Abstract: According to an embodiment of the disclosure, a method of fabricating a carrier for a wafer level package (WLP) by using a lead frame, wherein the lead frame is fabricated by forming a trench and a post by performing first half etching on an upper surface of a base substrate comprising a conductive material, filling the first-half-etched surface with resin of an insulating material, removing the resin exposed to outside of the trench so that an upper surface of the trench and an upper surface of the resin are at a same level, and performing second half etching on a lower surface of the base substrate, in which a memory chip is attached to the lower surface of the base substrate.

Abstract: Provided are a method of manufacturing a semiconductor package substrate, a semiconductor package substrate manufactured using the method of manufacturing a semiconductor package substrate, a method of manufacturing a semiconductor package, and a semiconductor package manufactured using the method of manufacturing a semiconductor package. The method of manufacturing a semiconductor package substrate includes forming first grooves or first trenches in a bottom surface of a base substrate having a top surface and the bottom surface and formed of a conductive material; filling the first grooves or trenches with resin; curing the resin; removing exposed portions of the resin overfilled in the first grooves or trenches; etching the top surface of the base substrate to expose at least portions of the resin filled in the first grooves or trenches; and forming a second groove or a second trench in the bottom surface of the base substrate.

Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench and a post by etching an upper surface of a base substrate including a conductive material, filling the trench with a resin, removing the resin exposed to outside of the trench such that an upper surface of the post and an upper surface of the resin are at same level, forming a conductive layer on an entire area of the upper surface of the post and the upper surface of the resin, and forming a circuit wiring including an upper circuit wiring and a lower circuit wiring by simultaneously patterning the conductive layer and a lower surface of the base substrate.

Abstract: A semiconductor package substrate, in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, includes a die pad formed of the conductive material on the upper surface and a lead arranged on the upper surface by being electrically separated from the die pad and comprising a bonding pad that is a wire bonding area. A protrusion protruding toward the lower surface is formed in a central area of the bonding pad. A central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.

Abstract: A semiconductor package substrate, in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, includes a die pad formed of the conductive material on the upper surface and a lead arranged on the upper surface by being electrically separated from the die pad and comprising a bonding pad that is a wire bonding area. A protrusion protruding toward the lower surface is formed in a central area of the bonding pad. A central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.

Abstract: Provided are a semiconductor package substrate and a manufacturing method thereof having improved pattern accuracy and product reliability with simple manufacturing processes. The semiconductor package substrate includes a base substrate having a conductive material, and including a first area, on which chips are mounted, including first recesses or first trenches in a surface, and a second area contacting the first area and including dummy recesses or dummy trenches in a surface; and a resin filled in the first recesses or the first trenches and the dummy recesses or the dummy trenches.

Abstract: A semiconductor package substrate, in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, includes a die pad formed of the conductive material on the upper surface and a lead arranged on the upper surface by being electrically separated from the die pad and comprising a bonding pad that is a wire bonding area. A protrusion protruding toward the lower surface is formed in a central area of the bonding pad. A central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.