Abstract: A super-steep switching device and an inverter device using the same are disclosed. The super-steep switching device includes a semiconductor channel disposed on a substrate and made of a semiconductor material having impact ionization characteristic; a source electrode and a drain electrode in contact with the semiconductor channel, wherein the source electrode and the drain electrode are disposed on the substrate and are spaced apart from each other; and a gate electrode disposed on the semiconductor channel so as to overlap only a portion of the semiconductor channel, wherein a top surface of the semiconductor channel includes a first area overlapping the gate electrode, and a second area non-overlapping the gate electrode, wherein a ratio of a length of the first area and a length of the second area is in a range of 1:0.1 to 0.4.

Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.

Abstract: A method of forming a capacitor having a lower electrode, an upper electrode, and a dielectric layer of an integrated circuit device is provided. A metal compound is adsorbed on the lower electrode by using a gaseous metal compound. A physisorbed metal compound on the lower electrode is purged by using an inert gas. The metal compound adsorbed on the lower electrode is oxidized with an oxidation gas to form a metal oxide. A gaseous product formed by oxidizing the metal compound is purged. Above steps are repeated to form a diffusion barrier layer of the metal oxide. The dielectric layer is formed of Ta2O5 on the diffusion barrier layer. A heat treatment is performed for the dielectric layer comprised of Ta2O5 under oxidation atmosphere. The steps are performed in a single atomic layer deposition chamber.

Abstract: A storage electrode has a truncated-conical “pipe-shaped” top section having a small inner diameter, mounted on a cylindrical base section having a large inner diameter. To fabricate the storage electrode, a buried contact plug is formed on a first insulating layer on a wafer, and an etching stop layer and a second insulating layer are formed on the first insulating layer. A third insulating layer is formed on the second insulating layer after implanting impurities into the second insulating layer. An opening is formed by anisotropically etching the third insulating layer and the second insulating layer using a photoresist pattern as an etching mask. A cleaning process is carried out such that the second insulating layer exposed through the opening is isotropically etched. After depositing polysilicon along a profile of the second and third insulating layers to a uniform thickness, the remaining third and second insulating layers are removed.

Abstract: A storage electrode has a truncated-conical “pipe-shaped” top section having a small inner diameter, mounted on a cylindrical base section having a large inner diameter. To fabricate the storage electrode, a buried contact plug is formed on a first insulating layer on a wafer, and an etching stop layer and a second insulating layer are formed on the first insulating layer. A third insulating layer is formed on the second insulating layer after implanting impurities into the second insulating layer. An opening is formed by anisotropically etching the third insulating layer and the second insulating layer using a photoresist pattern as an etching mask. A cleaning process is carried out such that the second insulating layer exposed through the opening is isotropically etched. After depositing polysilicon along a profile of the second and third insulating layers to a uniform thickness, the remaining third and second insulating layers are removed.

Abstract: A storage electrode has a truncated-conical “pipe-shaped” top section having a small inner diameter, mounted on a cylindrical base section having a large inner diameter. To fabricate the storage electrode, a buried contact plug is formed on a first insulating layer on a wafer, and an etching stop layer and a second insulating layer are formed on the first insulating layer. A third insulating layer is formed on the second insulating layer after implanting impurities into the second insulating layer. An opening is formed by anisotropically etching the third insulating layer and the second insulating layer using a photoresist pattern as an etching mask. A cleaning process is carried out such that the second insulating layer exposed through the opening is isotropically etched. After depositing polysilicon along a profile of the second and third insulating layers to a uniform thickness, the remaining third and second insulating layers are removed.

Abstract: In a method of forming a thin film using an atomic layer deposition (ALD) method, a thin film is formed on a substrate in cycles. Each cycle includes injecting a first reactant including an atom that forms the thin film and a ligand into a reaction chamber that includes the substrate, purging the first reactant, injecting a second reactant into the reaction chamber, and purging the second reactant. The thin film is formed by a chemical reaction between the atom that forms the thin film and a second reactant whose binding energy with respect to the atom that forms the thin film is larger than the binding energy of the ligand with respect to the atom that forms the thin film and the generation of by-products is prevented. The generation of a hydroxide by-product in the thin film is suppressed by using a material that does not include a hydroxide as the second reactant, purging the second reactant, and reacting the second reactant with a third reactant that includes hydroxide.

Abstract: A storage electrode has a truncated-conical “pipe-shaped” top section having a small inner diameter, mounted on a cylindrical base section having a large inner diameter. To fabricate the storage electrode, a buried contact plug is formed on a first insulating layer on a wafer, and an etching stop layer and a second insulating layer are formed on the first insulating layer. A third insulating layer is formed on the second insulating layer after implanting impurities into the second insulating layer. An opening is formed by anisotropically etching the third insulating layer and the second insulating layer using a photoresist pattern as an etching mask. A cleaning process is carried out such that the second insulating layer exposed through the opening is isotropically etched. After depositing polysilicon along a profile of the second and third insulating layers to a uniform thickness, the remaining third and second insulating layers are removed.

Abstract: A method for forming a dielectric layer of a semiconductor device is disclosed. A semiconductor wafer is loaded into a reaction chamber. A source gas mixture containing at least two mixed chemical reactants is introduced into the reaction chamber, thereby chemically adsorbing a portion of the source gas mixture onto a surface of the semiconductor wafer. The chamber is purged or pumped to remove physisorbed reactants therefrom. The source gas mixture chemically adsorbed on the surface of the semiconductor wafer is oxidized to form an atomic layer.

Abstract: A semiconductor device includes a first electrode formed of a silicon-family material, a dielectric layer formed by sequentially supplying reactants on the first electrode, and a second electrode having a work function larger than that of the first electrode, with the second electrode being formed on the dielectric layer. The first electrode and the second electrode can be a lower electrode and an upper electrode, respectively, in a capacitor structure. Also, the first electrode and the second electrode can be a silicon substrate and a gate electrode, respectively, in a transistor structure. A stabilizing layer, which is, for example, a silicon oxide layer, a silicon nitride layer, or a composite layer of the silicon oxide layer and the silicon nitride layer, for facilitating the formation of the dielectric layer by hydrophilizing the surface of the first electrode, may be formed on the first electrode. The dielectric layer can be formed by an atomic layer deposition method.

Abstract: A method of forming a capacitor having a lower electrode, an upper electrode, and a dielectric layer of an integrated circuit device is provided. A metal compound is adsorbed on the lower electrode by using a gaseous metal compound. A physisorbed metal compound on the lower electrode is purged by using an inert gas. The metal compound adsorbed on the lower electrode is oxidized with an oxidation gas to form a metal oxide. A gaseous product formed by oxidizing the metal compound is purged. Above steps are repeated to form a diffusion barrier layer of the metal oxide. The dielectric layer is formed of Ta2O5 on the diffusion barrier layer. A heat treatment is performed for the dielectric layer comprised of Ta2O5 under oxidation atmosphere. The steps are performed in a single atomic layer deposition chamber.

Abstract: A method for forming a dielectric layer of a semiconductor device is disclosed. A semiconductor wafer is loaded into a reaction chamber. A source gas mixture containing at least two mixed chemical reactants is introduced into the reaction chamber, thereby chemically adsorbing a portion of the source gas mixture onto a surface of the semiconductor wafer. The chamber is purged or pumped to remove physisorbed reactants therefrom. The source gas mixture chemically adsorbed on the surface of the semiconductor wafer is oxidized to form an atomic layer.