Abstract: The present disclosure relates to a data driver circuit capable of overcoming a limitation in frequency by correcting a skew between a clock and data even when a frequency and the number of channels are increased, and the data driver circuit according to an aspect may include a shift register configured output sampling signals in response to a clock, a first latch part configured to sample and latch data of each channel in response to each of the sampling signals, and a bi-directional deskew buffer part disposed between a stage of a first channel and a stage of a second channel belonging to the shift register and between a first latch of a first channel and a second latch of a second channel belonging to the first latch part and configured to buffer a clock input from the stage of the first channel.

Abstract: The present disclosure relates to a data driver circuit capable of overcoming a limitation in frequency by correcting a skew between a clock and data even when a frequency and the number of channels are increased, and the data driver circuit according to an aspect may include a shift register configured output sampling signals in response to a clock, a first latch part configured to sample and latch data of each channel in response to each of the sampling signals, and a bi-directional deskew buffer part disposed between a stage of a first channel and a stage of a second channel belonging to the shift register and between a first latch of a first channel and a second latch of a second channel belonging to the first latch part and configured to buffer a clock input from the stage of the first channel.