Abstract: A touch display device and a method of driving the same are disclosed. The touch display device includes: a touch display panel displaying an image and sensing a touch; a plurality of touch electrodes disposed on the touch display panel and divided into a plurality of blocks; a plurality of gate lines disposed on the touch display panel and overlapping the plurality of touch electrodes; and a touch display driving circuit supplying a common voltage to the plurality of touch electrodes and supplying a gate voltage to the plurality of gate lines, wherein the common voltage has a first voltage before and after a first compensation period corresponding to a high level period of the gate voltage supplied to one of the plurality of gate lines firstly overlapping one of the plurality of touch electrodes and has a second voltage lower than the first voltage during the first compensation period.

Abstract: A touch display device and a method of driving the same are disclosed. The touch display device includes: a touch display panel displaying an image and sensing a touch; a plurality of touch electrodes disposed on the touch display panel and divided into a plurality of blocks; a plurality of gate lines disposed on the touch display panel and overlapping the plurality of touch electrodes; and a touch display driving circuit supplying a common voltage to the plurality of touch electrodes and supplying a gate voltage to the plurality of gate lines, wherein the common voltage has a first voltage before and after a first compensation period corresponding to a high level period of the gate voltage supplied to one of the plurality of gate lines firstly overlapping one of the plurality of touch electrodes and has a second voltage lower than the first voltage during the first compensation period.

Abstract: A method of fabricating an array substrate, forming a gate line in a display region and a first auxiliary pattern in a non-display region forming a gate insulating layer on the gate line and the first auxiliary pattern forming a data line in the display region and a second auxiliary pattern in the non-display region over the gate insulating layer, wherein the data line crosses the gate line to define a pixel region forming a passivation layer on the data line and the second auxiliary pattern, and the passivation layer including first and second contact holes respectively exposing the first and second auxiliary patterns forming a planarization layer and a bridge pattern on the passivation layer forming a pixel electrode on the planarization layer and in the pixel region, and a connection pattern on the bridge pattern, wherein the connection pattern contacts the first and second auxiliary patterns.

Abstract: A method of fabricating an array substrate, forming a gate line in a display region and a first auxiliary pattern in a non-display region forming a gate insulating layer on the gate line and the first auxiliary pattern forming a data line in the display region and a second auxiliary pattern in the non-display region over the gate insulating layer, wherein the data line crosses the gate line to define a pixel region forming a passivation layer on the data line and the second auxiliary pattern, and the passivation layer including first and second contact holes respectively exposing the first and second auxiliary patterns forming a planarization layer and a bridge pattern on the passivation layer forming a pixel electrode on the planarization layer and in the pixel region, and a connection pattern on the bridge pattern, wherein the connection pattern contacts the first and second auxiliary patterns.

Abstract: An array substrate according to an embodiment includes a gate line and a data line in a display region and crossing each other to define a pixel region; first and second auxiliary patterns in a non-display region; a gate insulating layer between the gate and data lines and the first and second auxiliary patterns; a passivation layer on the data line and the second auxiliary pattern and including first and second contact holes respectively exposing the first and second auxiliary patterns; a planarization layer on the passivation layer and including first and second pack holes, which respectively correspond to the first and second contact holes; a bridge pattern between the first and second pack holes and overlapping the second auxiliary pattern; a pixel electrode on the planarization layer and in the pixel region; and a connection pattern on the bridge pattern and contacting the first and second auxiliary patterns.

Abstract: An array substrate according to an embodiment includes a gate line and a data line in a display region and crossing each other to define a pixel region; first and second auxiliary patterns in a non-display region; a gate insulating layer between the gate and data lines and the first and second auxiliary patterns; a passivation layer on the data line and the second auxiliary pattern and including first and second contact holes respectively exposing the first and second auxiliary patterns; a planarization layer on the passivation layer and including first and second pack holes, which respectively correspond to the first and second contact holes; a bridge pattern between the first and second pack holes and overlapping the second auxiliary pattern; a pixel electrode on the planarization layer and in the pixel region; and a connection pattern on the bridge pattern and contacting the first and second auxiliary patterns.