Patents by Inventor Sung-Jinn Chung

Sung-Jinn Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Impedance calibration circuit and semiconductor device including the same
    Patent number: 7408379
    Abstract: An impedance calibration circuit and a semiconductor device including the same are provided. An embodiment of the invention provides an impedance calibration circuit with a variable reference voltage generation unit. The impedance calibration circuit maximizes the number of semiconductor devices that can be tested in test equipment at one time and permits the operation of an impedance matching unit (e.g., an on-die-termination (ODT) circuit and/or an off-chip-driver (OCD)) to be tested for a variety of reference resistor values.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: August 5, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Ki Cho, Mi-Jin Lee, Sung-Jinn Chung
  • IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    Publication number: 20080143377
    Abstract: An impedance calibration circuit and a semiconductor device including the same are provided. An embodiment of the invention provides an impedance calibration circuit with a variable reference voltage generation unit. The impedance calibration circuit maximizes the number of semiconductor devices that can be tested in test equipment at one time and permits the operation of an impedance matching unit (e.g., an on-die-termination (ODT) circuit and/or an off-chip-driver (OCD)) to be tested for a variety of reference resistor values.
    Type: Application
    Filed: September 12, 2007
    Publication date: June 19, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Ki CHO, Mi-Jin LEE, Sung-Jinn CHUNG