Abstract: A method of providing a widget includes displaying a first widget indicating time, and displaying first information indicating an attribute of a second widget and second information specifying the first information based on a user's selection on the first widget. The second widget includes the first information and the second information.

Abstract: A method and an apparatus for checking a pipelined parallel cyclic redundancy is disclosed. In accordance with the method and the apparatus of the present invention, after an entire CRC (cyclic redundancy check) logic is divided into a feedback portion and an input data portion, the input data portion is divided using a pipelined structure such that the input data portion is designed to have the pipelined structure based on an algorithm that maintains a logic level of each stage to be lower than that of the feedback portion and an algorithm that optimizes a size of a register inserted during the division to improve a speed thereof and to detect an error of a received data in a high speed data communication apparatus.

Abstract: An interconnect delay fault test controller and a test apparatus using the same wherein an update operation and a capture operation may be carried out in one interval of a system clock or a core clock when carrying out an interconnect delay fault test between an IEEE P1500 wrapped cores in a SoC as well as an interconnect wire on a board based on an IEEE 1149.1, and wherein the interconnect delay fault test using different system clocks or core clocks may be carried out simultaneously in one test cycle corresponding to each system clock or core clock even when multiple system clocks or core clocks exists is disclosed.

Abstract: A system-on-chip (SoC) test apparatus is disclosed. The system-on-chip (SoC) testing apparatus reduces a test time due to a small amount of overhead in the case of testing an AMBA-based system-on-chip (SoC) using a TIC, an EBI, and a Test Harness, and maintains AMBA- or TIC- compatibility simultaneously while performing scan input/output operations.

Abstract: Provided is a 4× framer/deframer module for PCI-Express and a framer/deframer device using the same. In the PCI-Express for high-rate data processing, delimiter and pad processing, and 4× framer shifting and arrangement/reverse arrangement for framing/deframing a frame format are performed to achieve a structure that facilitates reconfiguration and expansion, for example, a pipeline structure, so that the 4× framer/deframer module can operate without delay within a 250 MHz clock even when expansion to 32× is made.

Abstract: A system-on-chip (SoC) test apparatus is disclosed. The system-on-chip (SoC) testing apparatus reduces a test time due to a small amount of overhead in the case of testing an AMBA-based system-on-chip (SoC) using a TIC, an EBI, and a Test Harness, and maintains AMBA- or TIC- compatibility simultaneously while performing scan input/output operations.

Abstract: Disclosed herein is an SoC-based core scan chain linkage switch. The core scan chain linkage switch includes test bus terminals, scan chain input/output terminals, a switch unit and SCLK, UCLK, Mode and Enable signals. The test bus terminals apply instructions and input/output test data. The scan chain input/output terminals link with the scan chains of an embedded core. The switch unit completes a linkage configuration between the test bus terminals and the scan chain input/output terminals in response to the applied instructions. The SCLK, UCLK and Mode signals apply the instructions to dynamically reconfigure the switch unit and update the linkage configuration of the switch unit, and the Enable signal activates and deactivates the switch unit.

Abstract: A method and an apparatus for checking a pipelined parallel cyclic redundancy is disclosed. In accordance with the method and the apparatus of the present invention, after an entire CRC (cyclic redundancy check) logic is divided into a feedback portion and an input data portion, the input data portion is divided using a pipelined structure such that the input data portion is designed to have the pipelined structure based on an algorithm that maintains a logic level of each stage to be lower than that of the feedback portion and an algorithm that optimizes a size of a register inserted during the division to improve a speed thereof and to detect an error of a received data in a high speed data communication apparatus.

Abstract: A wrapped core linking module for accessing system on chip test includes a link control register that stores link control configuration between cores in a scan path of a system on chip according to control signals applied from an outside boundary. A link control register controller controls a shift and update link configuration by activating the link control register. A switch switches the scan path between wrapped cores based on the link control configuration of the link control register. An output logic connects the link control register to a test data out (TDO) of the chip in case of testing on chip or cores of system on chip.

Abstract: An 8B/10B encoder/decoder including logic gates. The 8B/10B encoder including logic gates including a 5B/6B encoding block to compute 6 bit output data, in which the number of ‘0’s and the number of ‘1’s are balanced, from 5 bit input data; a 3B/4B encoding block to compute 4 bit output data, in which the number of ‘0’s and the number of ‘1’s are balanced, from 3 bit input data; and a disparity computation block to create and output a disparity in response to outputs and clocks of the 5B/6B encoding block and the 3B/4B encoding block. Thus, an 8B/10B encoder/decoder including logic gates uses a two-group logic combination method with emphasis on speed rather than size. The minimum number of stages for data processing at logic gate level guarantees more stable and fast operation.

Abstract: The present invention is an architecture of wrapped core linking module for accessing system on chip test which maintains compatibility of the IEEE 1149.1 standard with not only an IEEE 1149.1 boundary scan but also cores embodied by an IEEE P1500 wrapper and is able to systematically access the system on chip test with expandability.