Abstract: A novel compound for a capping layer, and an organic light-emitting device containing the same are disclosed.

Abstract: A novel compound for a capping layer, and an organic light-emitting device containing the same are disclosed.

Abstract: An inverter module according to an embodiment of the present invention comprises: a high voltage circuit unit which generates an inverter control voltage and a motor driving voltage by using a first DC voltage; a high voltage circuit pattern which electrically connects the high voltage circuit unit; a low voltage circuit unit which communicates with an external device by using a second DC voltage having a smaller magnitude than the first DC voltage; and a low voltage circuit pattern which electrically connects the low voltage circuit unit. The high voltage circuit pattern and the low voltage circuit pattern are spaced apart from each other.

Abstract: A light emitting device package, comprises a light emitting structure having first and second electrodes insulated from each other; and a support structure. The support structure comprises: a first support electrode electrically connected to the first electrode of the light emitting structure; a second support electrode electrically connected to the second electrode of the light emitting structure, the second support electrode spaced apart from, and electrically insulated from, the first support electrode; and a support connection portion between the first support electrode and the second support electrode. The light emitting structure includes a protrusion portion that protrudes in a horizontal direction beyond a sidewall of at least one of the first support electrode and the second support electrode so that a void is present below the protrusion portion and above a plane extending from bottoms of the first and second support electrodes.

Abstract: There is provided an electronic device package including an electronic device including a first electrode and a second electrode disposed on a surface thereof, a package substrate having a first surface having the electronic device mounted thereon and a second surface opposed to the first surface. The package substrate includes a first electrode pattern and a second electrode pattern electrically connected to the first electrode and the second electrode on the first surface, respectively. The package substrate further includes at least one via hole disposed outside of a region for mounting the electronic device and an irregular portion disposed on the first surface to be adjacent to the via hole.

Abstract: A method of manufacturing a semiconductor light emitting device package includes providing a wafer and forming, on the wafer, a semiconductor laminate comprising a plurality of light emitting devices. Electrodes are formed in respective light emitting device regions of the semiconductor laminate. A curable resin is applied to a surface of the semiconductor laminate on which the electrodes are formed. A support structure is formed for supporting the semiconductor laminate by curing the curable resin. Through holes are formed in the support structure to expose the electrodes therethrough. Connection electrodes are formed in the support structure to be connected to the exposed electrodes.

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract: A light emitting device package including a first electrode pad and a second electrode pad formed to contact a lower surface of a light emitting device; a bonded insulating layer pattern formed to at least partially cover side surfaces and lower surfaces of the first electrode pad and the second electrode pad; a substrate, in which via holes are formed which penetrate the substrate from a first surface of the substrate that contacts a lower surface of the bonded insulating layer pattern to a second surface of the substrate that is opposite to the first surface; a through-electrode disposed in each via hole and contacting the lower surface of one of the respective first electrode pad and the second electrode pad; and a through-electrode insulating layer formed between the through-electrode and the substrate, and having an upper surface that contacts a portion of the lower surface of the bonded insulating layer pattern.

Abstract: The present application provides an electronic device package. The package includes a packaging substrate having first and second surfaces opposing one another. First and second electrode patterns are formed on the first surface and first and second external terminals connected to the first and second electrode patterns. The second electrode pattern is electrically insulated from the first electrode pattern and surrounds the first electrode pattern An electronic device is mounted on the first surface of the packaging substrate and includes first and second electrodes disposed on a surface thereof facing the packaging substrate. The first and second electrodes are positioned on the first and second electrode patterns, respectively.

Abstract: A method of manufacturing a semiconductor light emitting device package includes providing a wafer and forming, on the wafer, a semiconductor laminate comprising a plurality of light emitting devices. Electrodes are formed in respective light emitting device regions of the semiconductor laminate. A curable resin is applied to a surface of the semiconductor laminate on which the electrodes are formed. A support structure is formed for supporting the semiconductor laminate by curing the curable resin. Through holes are formed in the support structure to expose the electrodes therethrough. Connection electrodes are formed in the support structure to be connected to the exposed electrodes.

Abstract: A semiconductor light emitting device package is provided having a light transmissive substrate, and a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer sequentially laminated on the light transmissive substrate. The light emitting structure comprises a first surface and a second opposing surface facing the light transmissive substrate. The semiconductor light emitting device package comprises a via penetrating the second conductivity-type semiconductor layer and the active layer, and exposing the first conductivity-type semiconductor layer. A first electrode has a first portion disposed on the first surface, and a second portion extending into the via and contacting the first conductivity-type semiconductor layer. An insulating layer is disposed between the first electrode, and each of the second conductivity type semiconductor layer, the active layer, and the first surface.

Abstract: There is provided an electronic device package including an electronic device including a first electrode and a second electrode disposed on a surface thereof, a package substrate having a first surface having the electronic device mounted thereon and a second surface opposed to the first surface. The package substrate includes a first electrode pattern and a second electrode pattern electrically connected to the first electrode and the second electrode on the first surface, respectively. The package substrate further includes at least one via hole disposed outside of a region for mounting the electronic device and an irregular portion disposed on the first surface to be adjacent to the via hole.

Abstract: A light emitting device package, comprises a light emitting structure having first and second electrodes insulated from each other; and a support structure. The support structure comprises: a first support electrode electrically connected to the first electrode of the light emitting structure; a second support electrode electrically connected to the second electrode of the light emitting structure, the second support electrode spaced apart from, and electrically insulated from, the first support electrode; and a support connection portion between the first support electrode and the second support electrode. The light emitting structure includes a protrusion portion that protrudes in a horizontal direction beyond a sidewall of at least one of the first support electrode and the second support electrode so that a void is present below the protrusion portion and above a plane extending from bottoms of the first and second support electrodes.

Abstract: The present application provides an electronic device package. The package includes a packaging substrate having first and second surfaces opposing one another. First and second electrode patterns are formed on the first surface and first and second external terminals connected to the first and second electrode patterns. The second electrode pattern is electrically insulated from the first electrode pattern and surrounds the first electrode pattern An electronic device is mounted on the first surface of the packaging substrate and includes first and second electrodes disposed on a surface thereof facing the packaging substrate. The first and second electrodes are positioned on the first and second electrode patterns, respectively.

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract: A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract: A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first

Abstract: A method of forming a semiconductor package includes attaching a semiconductor substrate on a support substrate, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region that separates respective ones of the semiconductor chips. A first cutting groove is formed that has a first kerf width between first and second ones of the plurality of first semiconductor chips. A plurality of second semiconductor chips is attached to the plurality of first semiconductor chips. A molding layer is formed so as to fill the first cutting groove and a second cutting groove having a second kerf width that is less than the first kerf width is formed in the molding layer so as to form individual molding layers covering one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chips.

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.