Abstract: A buffer flush controller, of a peripheral component interconnect-peripheral component interconnect bridge (PPB), includes a first compounding circuit, a first state machine, a second state machine, and a second compounding circuit. The buffer flush controller can maintain data consistency by efficiently controlling a flush operation of a data buffer of a peripheral component interconnect bridge, and the buffer flush controller can ensure a normal system operation without deadlock.

Abstract: A PCI bus arbiter is provided as an additional PCI bus in PCI peer-to-peer bus bridge system. A bus control system having the PCI bus arbiter is also provided. The bus control system includes bus masters, a first PCI bus bridge, a second PCI bus bridge, an EISA/ISA bus bridge for changing structures of signals from the bus masters to be suitable for corresponding bus, a first arbiter in a main chip set, and a second arbiter for arbitration process. The second arbiter includes an edge detecting state machine which detects whether a PCI bus is accessed by a bus master, and produces a frame-signal which changes a logic state thereof according to an access condition of the PCI bus. The second arbiter may also include a priority resolve state machine which receives the frame-signal and produces priority values which determine an order of bus masters to use the PCI bus, wherein the priority values are changed according to the frame-signal.

Abstract: An apparatus for detecting an operating state of a cooling fan in a computer system protects the computer system from damage due to excessive heat by preventing further operation of the computer system when the cooling fan is operating in an abnormal condition. The apparatus includes a pulse generating circuit for generating pulses in accordance with the motion of a cooling fan while the cooling fan revolves. A per revolution pulse generating circuit generates a pulse signal for every revolution of the cooling fan in accordance with the pulse signals provided from the pulse generating circuit. A dividing counter circuit outputs pulse signals having a specified period set in accordance with incoming data and reference clock signals. A revolution state determining circuit sets a time period for checking the operating state of the cooling fan in accordance with the pulse signals provided from the dividing counter circuit.