Patents by Inventor Sung-Kuang Wu

Sung-Kuang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8984354
    Abstract: A test system, comprising: a BIST circuit for generating a first signal; a storage apparatus, for storing the first signal to generate a second signal; a first logic circuit, for generating a third signal; a second logic circuit; a register; and a passby circuit. In a first mode, the BIST circuit transmits the first signal to the storage device, the storage device outputs the second signal to the register for registering, and then the register outputs the registered second signal to the BIST circuit to test the storage apparatus. In a second mode, the first logic circuit transmits a third signal to the register for registering, and then the register outputs the registered third signal to the second logic circuit.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: March 17, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventors: Shuo-Fen Kuo, Jih-Nung Lee, Sung-Kuang Wu
  • Patent number: 8479060
    Abstract: The present invention relates to a memory with a self-test function and a method for testing the same. The memory comprises a testing unit, a memory unit, and a comparison module. The method for testing the memory comprises steps of the testing unit producing a pattern signal; a first storage block of the memory unit storing storage data, and outputting the storage data according to the pattern signal; a second storage block of the memory storing a compare signature corresponding to the storage data; and the compare module producing a test signature according to the storage data output by the memory unit, and comparing the test signature to the compare signature and outputting a testing result for judging validity of the memory unit. Thereby, the memory unit according to the present invention is partitioned into two storage blocks for storing the storage data and the compare signature, respectively, and thus achieving the purposes of saving the testing time, costs, and hardware resources.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: July 2, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventors: Shuo-Fen Kuo, Jih-Nung Lee, Sung-Kuang Wu
  • Publication number: 20120304032
    Abstract: A test system, comprising: a BIST circuit for generating a first signal; a storage apparatus, for storing the first signal to generate a second signal; a first logic circuit, for generating a third signal; a second logic circuit; a register; and a passby circuit. In a first mode, the BIST circuit transmits the first signal to the storage device, the storage device outputs the second signal to the register for registering, and then the register outputs the registered second signal to the BIST circuit to test the storage apparatus. In a second mode, the first logic circuit transmits a third signal to the register for registering, and then the register outputs the registered third signal to the second logic circuit.
    Type: Application
    Filed: May 21, 2012
    Publication date: November 29, 2012
    Inventors: Shuo-Fen Kuo, Jih-Nung Lee, Sung-Kuang Wu
  • Publication number: 20110179323
    Abstract: The present invention relates to a memory with a self-test function and a method for testing the same. The memory comprises a testing unit, a memory unit, and a comparison module. The method for testing the memory comprises steps of the testing unit producing a pattern signal; a first storage block of the memory unit storing storage data, and outputting the storage data according to the pattern signal; a second storage block of the memory storing a compare signature corresponding to the storage data; and the compare module producing a test signature according to the storage data output by the memory unit, and comparing the test signature to the compare signature and outputting a testing result for judging validity of the memory unit. Thereby, the memory unit according to the present invention is partitioned into two storage blocks for storing the storage data and the compare signature, respectively, and thus achieving the purposes of saving the testing time, costs, and hardware resources.
    Type: Application
    Filed: January 17, 2011
    Publication date: July 21, 2011
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Shuo-Fen Kuo, Jih-Nung Lee, Sung-Kuang Wu