Abstract: Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.

Abstract: Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.

Abstract: Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.

Abstract: Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.

Abstract: Disclosed is a semiconductor memory device comprising: a memory cell array formed of cell blocks arranged in matrix of row and column; sub wordline drivers, interposed between the cell blocks arranged along column direction, each for driving a row of the cell blocks in response to a wordline drive signal; and wordline drive signal generators, disposed between the sub wordline drivers arranged along row direction, each for providing the wordline drive signal to the corresponding sub wordline driver. The wordline drive signal generators have different drive capabilities depending upon the number of wordline drivers to be driven by the generators.

Abstract: Disclosed is a semiconductor memory device comprising: a memory cell array formed of cell blocks arranged in matrix of row and column; sub wordline drivers, interposed between the cell blocks arranged along column direction, each for driving a row of the cell blocks in response to a wordline drive signal; and wordline drive signal generators, disposed between the sub wordline drivers arranged along row direction, each for providing the wordline drive signal to the corresponding sub wordline driver. The wordline drive signal generators have different drive capabilities depending upon the number of wordline drivers to be driven by the generators.