Abstract: Provided is a package substrate including a dielectric layer having a first surface and a second surface opposite to the first surface; an insulating layer formed on the first surface of the dielectric layer and having a plurality of grooves; a first circuit layer formed in the plurality of grooves and flush with the insulating layer; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive pillars formed in the dielectric layer and electrically connected to the first circuit layer and the second circuit layer. The present disclosure further provides a method of manufacturing the package substrate.

Abstract: A manufacturing method of an electronic package is provided, including: providing a circuit structure having a circuit layer; forming an insulating layer on the circuit structure, wherein the insulating layer has a plurality of first vias; forming a plurality of conductive pillars in the plurality of first vias, and disposing an electronic element on the insulating layer; forming an encapsulation layer, on the insulating layer, covering the electronic element and the plurality of conductive pillars, wherein the encapsulation layer has a plurality of second vias exposing the plurality of conductive pillars; and filling in the second vias with a plurality of conductive materials. The present disclosure further provides an electronic package.

Abstract: A package substrate is provided, in which a plurality of grooves are formed on a dielectric layer, so that a first circuit layer is embedded in the dielectric layer and is exposed from the grooves, wherein the depths of the plurality of grooves are uniform to facilitate embedding a plurality of solder balls in the plurality of grooves and bonding the plurality of solder balls to the first circuit layer.

Abstract: A package substrate is provided, in which dielectric layers are formed on a core board, and a wiring layer is embedded in at least one of the dielectric layers, so that the wiring layer has better copper adhesion to prevent delamination problems. A method of fabricating the package substrate is also provided.

Abstract: Provided is an electronic package, in which an external connection structure is formed on a first side of a circuit structure, at least one circuit assembly electrically connected to the circuit structure and at least one electronic element electrically connected to the circuit structure are disposed on a second side of the circuit structure, and the circuit assembly and the electronic element are encapsulated by a cladding layer. The coefficients of thermal expansion (CTEs) of the circuit assembly and the cladding layer are both greater than the CTE of the circuit structure, and the CTE of the circuit structure is greater than the CTE of the external connection structure, so as to prevent the difference in CTEs between the first side and the second side of the circuit structure from being significantly changed, thereby preventing the electronic package from warpage.

Abstract: An electronic package is provided, in which a cover layer is embedded in a circuit structure to form a groove, and an electronic element is disposed on the cover layer in the groove. A cladding layer encapsulates the electronic element, and an external connection structure is disposed on the circuit structure and the cladding layer. Therefore, the electronic element is embedded in the groove, such that a thickness of the electronic package can be greatly reduced to meet the requirement of thinning.

Abstract: A package substrate is provided and includes a core board body and a first circuit structure and a second circuit structure disposed on opposite sides of the core board body, where the number of wiring layers of the second circuit structure is different from the number of wiring layers of the first circuit structure, so that the package substrate is asymmetrical. The first circuit structure and the second circuit structure are designed according to the thickness and coefficient of thermal expansion of the first dielectric layer of the first circuit structure and the second dielectric layer of the second circuit structure, so as to prevent the problem of warping from occurring to the package substrate.

Abstract: A manufacturing method of a package substrate is provided, the manufacturing method includes forming a first circuit layer on a first metal layer; forming a dielectric layer on the first metal layer and the first circuit layer; forming a second metal layer on the dielectric layer; forming a plurality of conductive blind vias in the dielectric layer and forming a second circuit layer on the second metal layer, where the plurality of conductive blind vias are electrically connected to the first circuit layer and the second circuit layer; and removing the first metal layer and a portion of the second metal layer simultaneously. Therefore, in the manufacturing method, the first metal layer and the second metal layer can be removed by one etching process, such that the time for manufacturing the package substrate can be greatly reduced to increase production quantity.

Abstract: A package substrate and the manufacturing method thereof are provided. The method includes encapsulating a circuit layer and a conductive pillar on the circuit layer with an insulating layer, and then forming a groove in the insulating layer corresponding to the conductive pillar, so as to form a routing layer in the groove, so there is no need for drilling to make blind vias. Therefore, the alignment problem of conventional circuits and conductive blind vias can be avoided.