Abstract: A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.

Abstract: A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.

Abstract: A low-power, high-performance inverter circuit comprises first and second inverter circuit portions. The first portion comprises a first inverter, including a first pull-up element and a first pull-down element, for inverting an input signal, a first switching element connected between the first pull-down element and ground for switching the first inverter, and a first diode connected between the first pull-down element and ground in parallel with the first switching element. The second portion comprises a second inverter, including a second pull-up element and a second pull-down element, for inverting an input signal, a second switching element connected between the second pull-up element and a supply voltage terminal for switching the second inverter, and a second diode connected between the second pull-up element and the supply voltage terminal in parallel with the second switching element. An output of the first portion is connected to an input of the second portion.

Abstract: Disclosed is a method for fabricating a semiconductor device wherein boron-halo ion implantation is performed only to a bit-line contact part while masking a storage node contact part. The method comprises the steps of: performing a first ion implantation into the semiconductor substrate to control the threshold voltage Vt; forming a gate electrode on the semiconductor substrate in which the first ion implantation has been performed; performing a second ion implantation with a tilt of desired degree, using the gate electrode as a mask in order to control the threshold voltage; and performing a third ion implantation to form an LDD region in the substrate region at both sides of the gate electrode. In this method, the first ion implantation is performed at a range of below 90% of the whole doping concentration required to control the threshold voltage, and the second ion implantation is performed with a degree of below 30° and in two directions or four directions vertical to the gate electrode.

Abstract: A semiconductor device isolation structure and a fabricating method therefor are disclosed. The isolation structure includes a trench which is formed on an isolating region to define an active region. First, second, and third insulating layers are deposited in the trench. The second insulating layer has an etch selection ratio different from those of the first and third insulating layers. The edge portions of the third insulating layer which contact the side walls of the trench characteristically do not show any collapse. Therefore, when supplying a subthreshold voltage, a hump phenomenon does not occur. As a result, leakage current is kept from increasing, and the device refresh characteristic can be kept from deteriorating. Further, the third insulating layer covers the top edge portions of the trench. Therefore, the gate insulating layer (which is formed later) has a sufficient thickness. Therefore, yield voltage characteristics can be kept from deteriorating.

Abstract: The present invention relates to a method for fabricating a DRAM cell transistor having a trench isolation structure, which can prevent the reduction in effective channel length and the deterioration of a punch-through characteristic at the edge portion of a field oxide film, which is caused by the reduction in the potential barrier between a junction region and a channel region, which is caused because the channel doping concentration at the edge portion of the field oxide film is lowered due to a boron segregation effect caused by the field oxide film, as compared to the central portion of a channel region. According to the method of the present invention, an electrode structure having the same conductive type as that of a well region is formed within the field oxide film.

Abstract: The present invention relates to a method for fabricating a DRAM cell transistor having a trench isolation structure, which can prevent the reduction in effective channel length and the deterioration of a punch-through characteristic at the edge portion of a field oxide film, which is caused by the reduction in the potential barrier between a junction region and a channel region, which is caused because the channel doping concentration at the edge portion of the field oxide film is lowered due to a boron segregation effect caused by the field oxide film, as compared to the central portion of a channel region. According to the method of the present invention, an electrode structure having the same conductive type as that of a well region is formed within the field oxide film.

Abstract: Disclosed is a method for fabricating a semiconductor device wherein boron-halo ion implantation is performed only to a bit-line contact part while masking a storage node contact part. The method comprises the steps of: performing a first ion implantation into the semiconductor substrate to control the threshold voltage Vt; forming a gate electrode on the semiconductor substrate in which the first ion implantation has been performed; performing a second ion implantation with a tilt of desired degree, using the gate electrode as a mask in order to control the threshold voltage; and performing a third ion implantation to form an LDD region in the substrate region at both sides of the gate electrode. In this method, the first ion implantation is performed at a range of below 90% of the whole doping concentration required to control the threshold voltage, and the second ion implantation is performed with a degree of below 30° and in two directions or four directions vertical to the gate electrode.

Abstract: A semiconductor device isolation structure and a fabricating method therefor are disclosed. The isolation structure includes a trench which is formed on an isolating region to define an active region. First, second, and third insulating layers are deposited in the trench. The second insulating layer has an etch selection ratio different from those of the first and third insulating layers. The edge portions of the third insulating layer which contact the side walls of the trench characteristically do not show any collapse. Therefore, when supplying a subthreshold voltage, a hump phenomenon does not occur. As a result, leakage current is kept from increasing, and the device refresh characteristic can be kept from deteriorating. Further, the third insulating layer covers the top edge portions of the trench. Therefore, the gate insulating layer (which is formed later) has a sufficient thickness. Therefore, yield voltage characteristics can be kept from deteriorating.

Abstract: The present invention related to a method of fabricating a semiconductor device which prevents short channel hump due to the moisture in an insulating interlayer. The present invention includes the steps of forming a trench typed field oxide layer defining an active area in a field area of a semiconductor substrate of a first conductive type, forming a gate to the direction of device width wherein a gate oxide layer is inserted between the gate and semiconductor substrate, forming impurity regions in the semiconductor substrate at both sides of the gate by ion implantation with impurities of a second conductive type, forming an insulating interlayer covering the gate on the semiconductor substrate, and removing moisture contained in the insulating interlayer by thermal treatment.

Abstract: A semiconductor device isolation structure and a fabricating method therefor are disclosed. The isolation structure includes a trench which is formed on an isolating region to define an active region. First, second, and third insulating layers are deposited in the trench. The second insulating layer has an etch selection ratio different from those of the first and third insulating layers. The edge portions of the third insulating layer which contact the side walls of the trench characteristically do not show any collapse. Therefore, when supplying a subthreshold voltage, a hump phenomenon does not occur. As a result, leakage current is kept from increasing, and the device refresh characteristic can be kept from deteriorating. Further, the third insulating layer covers the top edge portions of the trench. Therefore, the gate insulating layer (which is formed later) has a sufficient thickness. Therefore, yield voltage characteristics can be kept from deteriorating.

Abstract: The present invention related to a method of fabricating a semiconductor device which prevents short channel hump due to the moisture in an insulating interlayer. The present invention includes the steps of forming a trench typed field oxide layer defining an active area in a field area of a semiconductor substrate of a first conductive type, forming a gate to the direction of device width wherein a gate oxide layer is inserted between the gate and semiconductor substrate, forming impurity regions in the semiconductor substrate at both sides of the gate by ion implantation with impurities of a second conductive type, forming an insulating interlayer covering the gate on the semiconductor substrate, and removing moisture contained in the insulating interlayer by thermal treatment.

Abstract: A semiconductor device and a method for fabricating the same are disclosed that reduce short channel effects to improve device characteristics. The semiconductor device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film and a lightly doped region formed in the semiconductor substrate at both sides of the gate electrode. A sidewall insulating film is formed at both sides of the gate electrode and a heavily doped impurity region is formed in the semiconductor substrate extending from the sidewall insulating film. Further, an insulating film is formed at sides of the heavily doped impurity region. The insulating film prevents impurity ions from the heavily doped impurity region from diffusing into the channel region of the device.

Abstract: A thin film transistor (TFT) and a method for manufacturing the same suitable for improving device characteristics by using a self-align technology are disclosed, the TFT including a substrate; a gate electrode having first and second sides on the substrate; a first conductive layer pattern formed on the substrate, wherein between the first conductive layer pattern and the first side of the gate electrode is a sidewall spacer; the sidewall spacer; a second conductive layer pattern formed on the substrate to be connected to the first conductive layer pattern; a gate insulating layer formed on the gate electrode; an active layer formed on the gate insulating layer, the sidewall spacer, the first conductive layer pattern, and the substrate; a source region formed in the active layer at the second side of the gate electrode; and a drain region formed on the active layer on the first conductive layer pattern.

Abstract: Barrier layers of an insulating material block the diffusion of the halo ions to an edge portion of the gate electrode, the halo ions being injected for improving short channel characteristic. The barrier layers prevent an increase of a threshold voltage of the device and improve electrical characteristics of the device.

Abstract: A memory device of the present invention provides a stable operation and low voltage characteristics. An access device receives first and second data signals on first and second data lines, respectively, and is coupled to first and second nodes. A drive device is coupled to the access device at the first and second nodes. A voltage shifting device is coupled to at least one of the first and second nodes to change a voltage of at least one of the first and second nodes. The access device includes a first access transistor coupled to the first data line and the first node. The access device also includes a second access transistor coupled to the second data line and the second node. The first and second access transistors are responsive to a control signal.

Abstract: Disclosed is a transistor structure having a semiconductor substrate with a active region and a field region, a recess region being defined by either the field region or the active region, a gate electrode formed on portions of the active and recess region, and impurity regions formed in the active region of the semiconductor substrate on either side of the gate electrode. The transistor structure has an active region with at least one groove formed therein, and the transistor structure being formed for a low voltage operation.

Abstract: A semiconductor device and a method for fabricating the same are disclosed that reduce short channel effects to improve device characteristics. The semiconductor device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film and a lightly doped region formed in the semiconductor substrate at both sides of the gate electrode. A sidewall insulating film is formed at both sides of the gate electrode and a heavily doped impurity region is formed in the semiconductor substrate extending from the sidewall insulating film. Further, an insulating film is formed at sides of the heavily doped impurity region. The insulating film prevents impurity ions from the heavily doped impurity region from diffusing into the channel region of the device.

Abstract: A thin film transistor (TFT) and a method for manufacturing the same suitable for improving device characteristics by using a self-align technology are disclosed, the TFT including a substrate; a gate electrode having first and second sides on the substrate; a first conductive layer pattern formed on the substrate, wherein between the first conductive layer pattern and the first side of the gate electrode is a sidewall spacer; the sidewall spacer; a second conductive layer pattern formed on the substrate to be connected to the first conductive layer pattern; a gate insulating layer formed on the gate electrode; an active layer formed on the gate insulating layer, the sidewall spacer, the first conductive layer pattern, and the substrate; a source region formed in the active layer at the second side of the gate electrode; and a drain region formed on the active layer on the first conductive layer pattern.