Abstract: Provided are an apparatus and method for supplying a light-emitting diode (LED) wafer that may quickly and accurately transfer LED wafers by acquiring position information of pockets in a carrier in which the LED wafers are to be seated. The apparatus may include a cassette in which a plurality of LED wafers are loaded, a carrier including a plurality of pockets in which the LED wafers are seated, an aligning unit to align the LED wafers that are to be seated in the carrier, a transfer robot to transfer the LED wafers from the cassette to the aligning unit, a picker to hold, in an adsorbed state, the LED wafers transferred to the aligning unit, or to release the adsorbed state, a capturing unit to fix the picker, and to acquire position information of the pockets, and an LED wafer loading robot to transfer the picker and the capturing unit from the aligning unit to the carrier.

Abstract: A nonvolatile memory device using a resistance material and a method of fabricating the same are provided. The nonvolatile memory device includes a switching element, and a data storage part electrically connected to the switching element. In the data storage part, a lower electrode is connected to the switching element, and an insulating layer is formed on the lower electrode to a predetermined thickness. The insulating layer has a contact hole exposing the lower electrode. A data storage layer is filled in the contact hole and the data storage layer is formed of transition metal oxide. An upper electrode is formed on the insulating layer and the data storage layer.

Abstract: The present general inventive concept describes a switching mode power supply (SMPS) and a method of supplying power by using the same. An SMPS that may be used in an image forming apparatus can include a transformation unit to transform an alternating-current (AC) voltage input to the SMPS, into at least one direct-current (DC) voltage by using a transformer, a first output voltage output unit to output the transformed DC voltage as a first output voltage of the SMPS, a first switching unit to prevent output of the second output voltage, and a second switching unit to prevent output of the second output voltage.

Abstract: A nonvolatile memory device using a resistance material and a method of fabricating the same are provided. The nonvolatile memory device includes a switching element, and a data storage part electrically connected to the switching element. In the data storage part, a lower electrode is connected to the switching element, and an insulating layer is formed on the lower electrode to a predetermined thickness. The insulating layer has a contact hole exposing the lower electrode. A data storage layer is filled in the contact hole and the data storage layer is formed of transition metal oxide. An upper electrode is formed on the insulating layer and the data storage layer.

Abstract: A nonvolatile memory device using a resistance material and a method of fabricating the same are provided. The nonvolatile memory device includes a switching element, and a data storage part electrically connected to the switching element. In the data storage part, a lower electrode is connected to the switching element, and an insulating layer is formed on the lower electrode to a predetermined thickness. The insulating layer has a contact hole exposing the lower electrode. A data storage layer is filled in the contact hole and the data storage layer is formed of transition metal oxide. An upper electrode is formed on the insulating layer and the data storage layer.

Abstract: An apparatus and method for connecting a processor to buses. The apparatus includes a multiplexer which, when addressing information indicating the address of a first memory connected to a synchronous data bus synchronized with a processor, from the processor is received, receives first data from the processor and transfers the received first data to the first memory through the synchronous data bus, or receives second data from the first memory through the synchronous data bus and transfers the received second data to the processor, and if address information indicating the address of a second memory connected to an asynchronous data bus not synchronized with the processor, from the processor is received, receives third data from the processor and transfers the third data to a buffer, or receives fourth data from the buffer and transfers the fourth data to the processor.

Abstract: A memory mapping method is provided for writing block data composed of a plurality of lines in first and second memories, each memory including at least two banks of the same number. The method maps the memories such that continuous even-numbered lines are written in different banks of different memories, and continuous odd-numbered lines are written in different banks of different memories when the block data is motion-compensated in a frame mode or a field mode. Accordingly, bank interleaving can be carried out in the respective memories and two memory channels can be simultaneously used to improve bus utilization efficiency and memory channel utilization efficiency.

Abstract: A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.

Abstract: An image forming apparatus and an image forming method are provided, in which a drum itself forms an electrostatic latent image corresponding to print data that is to be printed, on a surface of the drum, the electrostatic latent image is developed so as to generate a developed image, the developed image is transferred onto a printing medium, and the transferred image is fixed to the printing medium. Accordingly, the time required to print the print data is drastically reduced, it is possible to reduce the size of an image forming apparatus, and high quality print outs can be obtained.

Abstract: A data transmission method of a GPRS includes estimating a possibility of an impending stall state of a transmit window, transmitting a stall state alarm signal of the transmit window to a network if it is predicted that the stall state of the transmit window is approaching, and controlling data transmissions according to whether an ACK signal for the stall state alarm signal is received or not from the network. Notification of the possibility of the stall state of the transmit window is provided at least once and preferably twice to the network before stall actually occurs, thereby reducing the number of occurrences of the transmit window's stall state. As a result, waste of network resources due to re-transmission performed in the stall state is minimized.

Abstract: A method and apparatus for encoding and/or decoding an image are provided. The method of encoding an image includes: generating a prediction block that is an intra or inter prediction value of a current block; calculating a color difference between the current block and the generated prediction block; and, encoding the current block by adjusting a quantization step, based on the calculated color difference. In this way, color distortion in a restored image that can occur when a color of a current block is incorrectly predicted can be prevented.

Abstract: A multi-display system and a method thereof which solves an overloading problem on a memory bus. The multi-display system includes displays which independently display separate images, a main memory which stores input image signals, image signal process units which are disposed corresponding to the displays and process the image signals according to the corresponding displays, a secondary memory which stores the image signals processed by the image signal process units, and a controller which controls the image signal process units to display the image signals stored in the main memory on each of the corresponding displays. The controller controls the image signal process units to display the image signals stored in the secondary memory on some of the displays in response to overloading of the image signals on the memory bus, through which the image signals are retrieved from, where the image signals are displayed on more than two displays.

Abstract: A memory mapping method is provided for writing block data composed of a plurality of lines in first and second memories, each memory including at least two banks of the same number. The method maps the memories such that continuous even-numbered lines are written in different banks of different memories, and continuous odd-numbered lines are written in different banks of different memories when the block data is motion-compensated in a frame mode or a field mode. Accordingly, bank interleaving can be carried out in the respective memories and two memory channels can be simultaneously used to improve bus utilization efficiency and memory channel utilization efficiency.

Abstract: An apparatus which processes a digital image and a method therefor which can reduce an error when calculating an output value obtained by interpolating pixel values of the input digital image. The apparatus includes an interpolation processing unit which interpolates an input digital image, and a controller which measures an interpolation interval of pixel values of the digital image, calculates a coefficient by substituting the interpolation interval for a coefficient equation stored in a register, and calculates an interpolation node for the digital image by substituting the coefficient and an output pixel position value of the digital image for an interpolation node calculation equation. The controller controls the interpolation processing unit so as to interpolate the digital image to the interpolation node. As a result, it is possible to reduce an error between an interpolated output pixel position value and an output pixel position value for the pixel values of the input digital image.

Abstract: A system-on-chip (SOC) based on an advanced micro-controller bus architecture (AMBA), and particularly, a bus connection method, is provided. The bus connection method includes: allowing one of a plurality of masters to use a plurality of slaves; generating information necessary for using the slaves by decoding a command generated by the master allowed to use the slaves; and outputting signals with reference to the generated information according to a protocol of a bus system to which the slaves are connected. Accordingly, it is possible to transmit data in a pipeline approach by applying bank interleaving to an occasion when only one master issues a request for the reading or writing of data in units of blocks.

Abstract: A nonvolatile memory device using a resistance material and a method of fabricating the same are provided. The nonvolatile memory device includes a switching element, and a data storage part electrically connected to the switching element. In the data storage part, a lower electrode is connected to the switching element, and an insulating layer is formed on the lower electrode to a predetermined thickness. The insulating layer has a contact hole exposing the lower electrode. A data storage layer is filled in the contact hole and the data storage layer is formed of transition metal oxide. An upper electrode is formed on the insulating layer and the data storage layer.

Abstract: A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.

Abstract: A SONOS type memory includes a semiconductor substrate, first and second impurity regions in the semiconductor substrate doped with impurity ions of a predetermined conductivity, separated a predetermined distance from each other, a channel region between the first and second impurity regions, and a data storage type stack on the semiconductor substrate between the first and second impurity regions. The data storage type stack includes a tunneling oxide layer, a memory node layer for storing data, a blocking oxide layer, and an electrode layer, which are sequentially formed. A dielectric constant of the memory node layer is higher than dielectric constants of the tunneling and the blocking oxide layers, and a band offset of the memory node layer is lower than band offsets of the tunneling and the blocking oxide layers. The tunneling oxide layer and the blocking oxide layer are high dielectric insulating layers.

Abstract: Provided are a method and apparatus for accelerating graphic data which can reduce the computational complexity of graphic processing data. The method of accelerating two-dimensional graphic data includes: receiving information regarding the width of a graphic window to be processed; reading pixel data from a memory in which pixel data in the graphic window is stored; receiving information regarding two pixel data regions which are divided from the memory area based on the width information of the graphic window, one pixel data region to be processed using a burst mode and the other pixel data region to be processed in units of bytes; and individually performing predetermined graphic processing on the divided pixel data regions.

Abstract: A SONOS type memory includes a semiconductor substrate, first and second impurity regions in the semiconductor substrate doped with impurity ions of a predetermined conductivity, separated a predetermined distance from each other, a channel region between the first and second impurity regions, and a data storage type stack on the semiconductor substrate between the first and second impurity regions. The data storage type stack includes a tunneling oxide layer, a memory node layer for storing data, a blocking oxide layer, and an electrode layer, which are sequentially formed. A dielectric constant of the memory node layer is higher than dielectric constants of the tunneling and the blocking oxide layers, and a band offset of the memory node layer is lower than band offsets of the tunneling and the blocking oxide layers. The tunneling oxide layer and the blocking oxide layer are high dielectric insulating layers.