Abstract: A thin film transistor array panel is provided, which includes: an insulating substrate; a plurality of first signal lines formed on the insulating substrate; a plurality of second signal lines formed on the insulating substrate and intersecting the first wire in an insulating manner; a pixel electrode formed in a pixel area defined by the intersections of the first signal lines and the second signal lines and including a plurality of subareas partitioned by cutouts and a plurality of bridges connecting the subareas; and a direction control electrode formed in the pixel area and including a portion overlapping at least one of the cutouts, wherein two long edges of each subarea are parallel to each other and the at least one of cutouts overlapping the portion of the direction control electrode defines one of two longest edges of the subarea.

Abstract: An array substrate includes a gate line, a data line, a switching device, a transmissive electrode, a reflective electrode and a compensating wiring. A pixel region includes first and second regions. The switching device is connected to the gate line and the data line. The transmissive electrode is connected to the switching device. The transmissive electrode is formed in the first region. The reflective electrode is insulated from the transmissive electrode. The reflective electrode is formed in the second region that is adjacent to the first region. The compensating wiring is connected to the switching device. The compensating wiring faces the reflective electrode in the second region with an insulation layer interposed therebetween. Thus, both of a reflectivity of the reflective electrode and a transmissivity of the transmissive electrode are enhanced simultaneously, while the liquid crystal display apparatus maintains a uniform cell gap.

Abstract: A thin film transistor array panel is provided, which includes: a pair of first and second gate lines; a data line intersecting the gate lines in an insulating manner; a storage electrode line supplied with a common voltage; a pixel electrode formed in a pixel area defined by the intersections of the first and the second gate lines and the data line and including a plurality of subareas partitioned by cutouts; a direction control electrode formed in the pixel area and including a portion overlapping at least one of the cutouts; a first thin film transistor connected to the pixel electrode, the first signal line, and the third signal line; a second thin film transistor connected to the pixel electrode, the second signal line, and the third signal line; and a third thin film transistor connected to the direction control electrode, the second signal line, and the fourth signal line.

Abstract: A thin film transistor array panel is provided, which includes: an insulating substrate; a first signal wire formed on the insulating substrate; a second signal wire formed on the insulating substrate and intersecting the first signal wire in an insulating manner; first and second pixel electrodes formed in a pixel area defined by the intersections of the first and the second signal wires and including a plurality of subareas partitioned by cutouts; a direction control electrode formed in the pixel area and including a portion overlapping at least one of the cutouts; and a first thin film transistor connected to the direction control electrode, the first signal wire, and the second signal wire.

Abstract: A thin film transistor array panel including a substrate; a gate line formed on the substrate; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a data line formed on the semiconductor layer; a drain electrode separated from the data line and formed on the semiconductor layer; a coupling electrode connected to the drain electrode; a first subpixel electrode connected to the drain electrode; and a second subpixel electrode separated from the first subpixel electrode and overlapping the coupling electrode.

Abstract: A thin film transistor array panel is provided, which includes: a gate wire formed on an insulating substrate; a data wire formed on the insulating substrate, insulated from the gate wire, and intersecting the gate wire; a storage electrode wire formed on the insulating substrate, insulated from the data wire, and intersecting the data wire; a plurality of pixel electrodes provided on the respective pixel areas defined by the intersections of the gate wire and the data wire, each pixel electrode having a cutout; a plurality of direction control electrodes provided on the respective pixel areas defined by the intersections of the gate wire and the data wire; a plurality of first thin film transistors connected to the gate wire, the data wire, and the pixel electrodes; and a plurality of second thin film transistors connected to the gate wire, the storage electrode wire, and the direction control electrodes.

Abstract: A thin film transistor array panel is provided, which includes: an insulating substrate; a first signal wire formed on the insulating substrate; a second signal wire formed on the insulating substrate and intersecting the first signal wire in an insulating manner; first and second pixel electrodes formed in a pixel area defined by the intersections of the first and the second signal wires and including a plurality of subareas partitioned by cutouts; a direction control electrode formed in the pixel area and including a portion overlapping at least one of the cutouts; and a first thin film transistor connected to the direction control electrode, the first signal wire, and the second signal wire.

Abstract: Gate lines are formed on an insulating substrate, and data lines crossing the gate lines are formed. The gate lines and the data lines are insulated from each other and intersect each other to define pixel areas. A thin film transistor including three terminals of a gate electrode, a source electrode and a drain electrode is formed in each pixel area. A direction control electrode and a pixel electrode are also formed in each pixel area. The thin film transistor switches the direction control electrode. The pixel electrode is electronically floating and capacitively coupled with the direction control electrode.

Abstract: A liquid crystal display is provided, which includes: first and second panels facing each other, interposing a gap therebetween, and first and second field generating electrodes, respectively; a liquid crystal layer filled in the gap and including a plurality of liquid crystal molecules; first and second tilt direction defining members disposed on the first and the second panels, respectively, and giving a first tilt direction to a group of the liquid crystal molecules; and a third tilt direction defining member disposed on one of the first and the second panels and giving a second tilt direction oblique to the first tilt direction to the group of the liquid crystal molecules.

Abstract: A pixel electrode and a direction control electrode capacitively coupled to the pixel electrode are provided in a pixel. A pixel thin film transistor is connected to a gate line, a data line, and the pixel electrode. A direction control electrode thin film transistor is connected to a previous gate line, a previous data lines or a next data line, and the direction control electrode. The gate lines are supplied with scanning signals, and each scanning signal includes first and second pulses in a frame. The first pulse of a scanning signal is synchronized with the second pulse of a previous scanning signal.

Abstract: A thin film transistor array panel is provided, which includes: a pair of first and second gate lines; a data line intersecting the gate lines in an insulating manner; a storage electrode line supplied with a common voltage; a pixel electrode formed in a pixel area defined by the intersections of the first and the second gate lines and the data line and including a plurality of subareas partitioned by cutouts; a direction control electrode formed in the pixel area and including a portion overlapping at least one of the cutouts; a first thin film transistor connected to the pixel electrode, the first signal line, and the third signal line; a second thin film transistor connected to the pixel electrode, the second signal line, and the third signal line; and a third thin film transistor connected to the direction control electrode, the second signal line, and the fourth signal line.

Abstract: A thin film transistor array panel is provided, which includes: an insulating substrate; a first signal wire formed on the insulating substrate; a second signal wire formed on the insulating substrate and intersecting the first signal wire in an insulating manner; first and second pixel electrodes formed in a pixel area defined by the intersections of the first and the second signal wires and including a plurality of subareas partitioned by cutouts; a direction control electrode formed in the pixel area and including a portion overlapping at least one of the cutouts; and a first thin film transistor connected to the direction control electrode, the first signal wire, and the second signal wire.

Abstract: A laundry net is diclosed which includes a net body formed into an octahedron, which is made by stitching four net members of a rhombic shape together, resulting in a stitched section being formed between each adjacent two net members. Also, the net includes a slide fastener including a slider with a lug and arranged at one of the stitched section and covers arranged at the portion of the one stitched section at which the slide fastener is positioned when the slide fastener is closed. The slider and lug are covered with the overlap portion between the covers. Such construction of the laundry net not only permits water to constantly flow into the net body and through the interior of the net body irrespective of its position with respect to the flow of water in the wash tub of the washing machine, so that the washing in the net body may be positively contacted with the flowing water but effectively prevents the slider and lug from damaging washing outside the laundry net.