Patents by Inventor Sung-Li Wang

Sung-Li Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230154845
    Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.
    Type: Application
    Filed: January 3, 2023
    Publication date: May 18, 2023
    Inventors: Sung-Li Wang, Yasutoshi Okuno
  • Publication number: 20230154758
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate, depositing a metal-rich metal silicide layer on the source/drain region, depositing a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and forming a contact plug on the silicon-rich metal silicide layer. This disclosure also describes a semiconductor device including a fin structure on a substrate, a source/drain region on the fin structure, a metal-rich metal silicide layer on the source/drain region, a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and a contact plug on the silicon-rich metal silicide layer.
    Type: Application
    Filed: January 16, 2023
    Publication date: May 18, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sung-Li WANG, Yasutoshi OKUNO, Shih-Chuan CHIU
  • Publication number: 20230124549
    Abstract: An exemplary method includes forming a semiconductor fin having a semiconductor layer stack over a semiconductor mesa. The semiconductor layer stack includes a first semiconductor layer, a second semiconductor layer, and the first semiconductor layer is between the semiconductor mesa and the second semiconductor layer. The method further includes forming an isolation feature adjacent the semiconductor mesa and forming a semiconductor cladding layer along a sidewall of the semiconductor layer stack. The semiconductor cladding layer extends below a top surface of the semiconductor mesa and a portion of the isolation feature is between the semiconductor cladding layer and a sidewall of the semiconductor mesa. The method further includes, in a channel region, replacing the first semiconductor layer of the semiconductor fin and the semiconductor cladding layer with a gate stack. The portion of the isolation feature is between the gate stack and the sidewall of the semiconductor mesa.
    Type: Application
    Filed: March 11, 2022
    Publication date: April 20, 2023
    Inventors: Cheng-Wei Chang, Shahaji B. More, Yi-Ying Liu, Shuen-Shin Liang, Sung-Li Wang
  • Patent number: 11626494
    Abstract: A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least one channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hung Chu, Sung-Li Wang, Shuen-Shin Liang, Hsu-Kai Chang, Ding-Kang Shih, Tsungyu Hung, Pang-Yen Tsai, Keng-Chu Lin
  • Publication number: 20230095976
    Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.
    Type: Application
    Filed: December 5, 2022
    Publication date: March 30, 2023
    Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG
  • Patent number: 11610888
    Abstract: A semiconductor device includes a semiconductive substrate, a semiconductive fin, an isolation structure, a source/drain epitaxial structure, a first cap layer, and a second cap layer. The semiconductive fin protrudes from the semiconductive substrate. The isolation structure is over the semiconductive substrate and laterally surrounds the semiconductive fin. The source/drain epitaxial structure is over the semiconductive fin. The source/drain epitaxial structure has a rounded corner extending laterally and a top above the rounded corner. The first cap layer extends from the rounded corner of the source/drain epitaxial structure to the top of the source/drain epitaxial structure. The second cap layer covers the rounded corner and a bottom of the source/drain epitaxial structure. The first and second cap layers are made of different materials.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Pang-Yen Tsai, Yasutoshi Okuno
  • Publication number: 20230061022
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure and over the gate structure, a layer of organometallic material formed through the layer of dielectric material, and a trench conductor layer formed through the layer of dielectric material and in contact with the S/D contact structure and the gate structure. The layer of organometallic material can be between the layer of dielectric material and the trench conductor layer.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsu-Kai CHANG, Chia-Hung CHU, Shuen-Shin LIANG, Keng-Chu LIN, Pinyen LIN, Sung-Li WANG
  • Publication number: 20230068965
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hung CHU, Shuen-Shin LIANG, Hsu-Kai CHANG, Tzu Pei CHEN, Kan-Ju LIN, Chien CHANG, Hung-Yi HUANG, Sung-Li WANG
  • Patent number: 11594609
    Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: February 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin Liang, Chun-I Tsai, Chih-Wei Chang, Chun-Hsien Huang, Hung-Yi Huang, Keng-Chu Lin, Ken-Yu Chang, Sung-Li Wang, Chia-Hung Chu, Hsu-Kai Chang
  • Publication number: 20230053595
    Abstract: A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Inventors: Sheng-Tsung WANG, Lin-Yu HUANG, Cheng-Chi CHUANG, Sung-Li WANG, Chih-Hao WANG
  • Patent number: 11581259
    Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Chien-Shun Liao, Sung-Li Wang, Shuen-Shin Liang, Shu-Lan Chang, Yi-Ying Liu, Chia-Hung Chu, Hsu-Kai Chang
  • Publication number: 20230030411
    Abstract: A fin field effect transistor device structure includes a fin structure formed over a substrate. The fin field effect transistor device structure also includes a source/drain epitaxial structure formed over the fin structure. The fin field effect transistor device structure also includes a contact structure with a concave top surface formed over the source/drain epitaxial structure. The fin field effect transistor device structure also includes a barrier layer conformally wrapped around the contact structure. The fin field effect transistor device structure also includes a via structure formed over the contact structure. The concave top surface of the contact structure is below the top surface of the barrier layer.
    Type: Application
    Filed: October 17, 2022
    Publication date: February 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hung CHU, Sung-Li WANG, Fang-Wei LEE, Jung-Hao CHANG, Mrunal Abhijith KHADERBAD, Keng-Chu LIN
  • Publication number: 20230029002
    Abstract: The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.
    Type: Application
    Filed: January 18, 2022
    Publication date: January 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chin Chang, Lin-Yu Huang, Shuen-Shin Liang, Sheng-Tsung Wang, Cheng-Chi Chuang, Chia-Hung Chu, Tzu Pei Chen, Yuting Cheng, Sung-Li Wang
  • Patent number: 11563083
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: January 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Shuen-Shin Liang, Sung-Li Wang, Hsu-Kai Chang, Chia-Hung Chu, Chien-Shun Liao, Yi-Ying Liu
  • Publication number: 20230016515
    Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Chien-Shun Liao, Sung-Li Wang, Shuen-Shin Liang, Shu-Lan Chang, Yi-Ying Liu, Chia-Hung Chu, Hsu-Kai Chang
  • Publication number: 20230016100
    Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 19, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO.,LTD.
    Inventors: Hsu-Kai CHANG, Keng-Chu LIN, Sung-Li WANG, Shuen-Shin LIANG, Chia-Hung CHU
  • Patent number: 11557484
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate, depositing a metal-rich metal silicide layer on the source/drain region, depositing a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and forming a contact plug on the silicon-rich metal silicide layer. This disclosure also describes a semiconductor device including a fin structure on a substrate, a source/drain region on the fin structure, a metal-rich metal silicide layer on the source/drain region, a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and a contact plug on the silicon-rich metal silicide layer.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: January 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sung-Li Wang, Yasutoshi Okuno, Shih-Chuan Chiu
  • Publication number: 20230009077
    Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The method includes forming first and second fin structures on a substrate, forming n- and p-type source/drain (S/D) regions on the first and second fin structures, respectively, forming first and second contact openings on the n- and p-type S/D regions, respectively, forming a carbon-based layer in the first and second contact openings, performing a remote plasma treatment with radicals on the carbon-based layer to form a remote plasma treated layer, selectively removing a portion of the remote plasma treated layer, forming a p-type work function metal (pWFM) silicide layer on the p-type S/D region, and forming an n-type work function metal (nWFM) silicide layer on the pWFM silicide layer and on the n-type S/D region.
    Type: Application
    Filed: February 25, 2022
    Publication date: January 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Huan-Chieh SU, Lo-Heng CHANG, Shih-Chuan CHIU, Hsu-Kai CHANG, Ko-Feng CHEN, Keng-Chu LIN, Pinyen LIN, Sung-Li WANG
  • Publication number: 20230009981
    Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.
    Type: Application
    Filed: February 16, 2022
    Publication date: January 12, 2023
    Inventors: Cheng-Wei CHANG, Chia-Hung CHU, Hsu-Kai CHANG, Sung-Li WANG, Kuan-Kan HU, Shuen-Shin LIANG, Kao-Feng LIN, Hung Pin LU, Yi-Ying LIU, Chuan-Hui SHEN
  • Publication number: 20230012147
    Abstract: The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.
    Type: Application
    Filed: July 9, 2021
    Publication date: January 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hung CHU, Ding-Kang SHIH, Keng-Chu LIN, Pang-Yen TSAI, Sung-Li WANG, Shuen-Shin LIANG, Tsungyu HUNG, Hsu-Kai CHANG