Abstract: The present invention relates to a secondary battery comprising a cathode, an anode and a separator interposed between the cathode and the anode, wherein the anode comprises an anode current collector and an anode mixture layer formed on at least one surface of the anode current collector, the anode mixture layer comprises an anode active material, a binder, and a conductive material, a loading amount of the anode mixture layer is 5 mg/cm2 to 15 mg/cm2 and value R of the anode mixture layer is 3,000 or less, wherein R means (permeability of the anode mixture layer)×(current density of a battery)2. According to the present invention, an overvoltage phenomenon of an anode surface and the deposition of lithium metal caused thereby can be prevented so that charging can be performed with a higher current, and thus rapid charging performance is improved, and lifespan is excellent even in the same current.

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

Abstract: A lamp for a vehicle forms a rear road surface pattern when the vehicle moves backward. The lamp for the vehicle includes a light source unit configured to generate light, a shield unit configured to selectively transmit a portion of the light generated from the light source unit, and a lens unit configured to concentrate the light transmitted through the shield unit onto a road surface. The lens unit includes a first lens part and a second lens part, and the second lens part includes an inner space through which the light emitted from the light source unit is transmitted.

Abstract: An apparatus and a method for transmitting HARQ feedback information in a wireless communication system are provided. In so doing, the method for transmitting the HARQ feedback information in a receiving end includes confirming the number of packets received from a transmitting end, and when receiving a reference number of packets from the transmitting end, transmitting to the transmitting end a feedback signal comprising HARQ feedback information for the reference number of the packets.

Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

Abstract: The manufacturing method of a palladium transition metal core-based core-shell electrode catalyst according to an exemplary embodiment of the present disclosure includes a first step of preparing a slurry by irradiating ultrasonic wave to a dispersion solution including a solvent, a platinum precursor, a palladium precursor, a carbon support, and a transition metal precursor, a second step of preparing a solid material by filtering, washing, and drying the slurry prepared in the first step, and a third step of preparing a core-shell electrode catalyst by thermally treating the solid prepared in the second step in a specific gas atmosphere.

Abstract: A method of manufacturing a dry electrode sheet for a secondary battery includes providing a dry electrode composition including an electrode active material and a binder, kneading the dry electrode composition, and manufacturing an electrode sheet by calendering the kneaded dry electrode composition.

Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure.

Abstract: A semiconductor system includes a controller configured to apply a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device including a first rank and a second rank configured to calibrate each termination resistance, based on the command address, the first chip selection signal, and the second chip selection signal.

Abstract: A semiconductor system includes a controller configured to transmit a command address and a plurality of read strobe signals, and a semiconductor device including a first rank and a second rank that are configured to receive the command address and the plurality of read strobe signals and to perform a write operation and a read operation based on the command address. In the semiconductor device, the first rank is configured to calibrate a termination resistance value of the first rank to a target resistance value when a write operation for the first rank is performed. In the semiconductor device, the first rank is configured to calibrate the termination resistance value of the first rank to a dynamic resistance value based on the plurality of read strobe signals when a write operation for the second rank is performed.

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

Abstract: The present disclosure provides compounds of Formula (I); or a pharmaceutically acceptable salt thereof, wherein each of Ring A, Ring B, Ra, Rb, L, R1, R2, m, and n is defined herein, pharmaceutical compositions thereof, methods of inhibiting ROCK1 and/or ROCK2, and methods of treating a ROCK1- and/or ROCK2-mediated disease or disorder.

Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

Abstract: The nonvolatile memory device includes a substrate including a first surface and a second surface opposite to the first surface in a first direction; a common source line on the first surface of the substrate; a plurality of word lines stacked on the common source line; a first insulating pattern spaced apart from the plurality of word lines in a second direction crossing the first direction, and in the substrate; an insulating layer on the second surface of the substrate; a first contact plug penetrating the first insulating pattern and extending in the first direction; a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plug; an upper bonding metal connected to the first contact plug and connected to a circuit element; and a first input/output pad connected to the second contact plug and electrically connected to the circuit element.

Abstract: A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.

Abstract: Provided is a primer composition including a thickener that contains at least one functional group selected from the group consisting of a hydroxyl group and a carboxyl group. The primer composition includes a thickener undissolved residue of 0.05 wt % or less based on the total solid weight thereof; an anode and a secondary battery including the same. A method for manufacturing the anode is also provided.

Abstract: A three-dimensional semiconductor memory device and an electronic system including the same are discussed. The device may include: a stack structure including electrode layers and inter-electrode insulating layers that are alternately stacked on a substrate; one or more vertical semiconductor structures that extend into the stack structure and are adjacent to the substrate; one or more vertical conductive structures arranged in a first direction between adjacent ones of the one or more vertical semiconductor structures and extending into the stack structure and are adjacent to the substrate; and a conductive line portion on the stack structure that extends in the first direction to connect the one or more vertical conductive structures to each other. The conductive line portion and the vertical conductive structures may be connected to form a single unit.