Abstract: An embodiment solid electrolyte includes a first compound and a second compound. The first compound is represented by a first chemical formula Li7-aPS6-a(X11-bX2b)a, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, and wherein 0<a?2 and 0<b<1, and the second compound is represented by a second chemical formula Li7-cP1-2dMdS6-c-3d(X11-eX2e)c, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, wherein M represents Ge, Si, Sn, or any combination thereof, and wherein 0<c?2, 0<d<0.5, and 0<e<1.

Abstract: A semiconductor device is provided. The semiconductor device includes an active pattern extending in a first horizontal direction, a plurality of lower nanosheets stacked on the active pattern and spaced apart from one another in a vertical direction, a separation layer on the plurality of lower nanosheets, a plurality of upper nanosheets stacked on the separation layer and spaced apart from one another in the vertical direction, a gate electrode extending on the active pattern in a second horizontal direction, the gate electrode surrounding each of the plurality of lower nanosheets, the separation layer and the plurality of upper nano sheets, and a first conductive layer between the gate electrode and each of a top surface and a bottom surface of the plurality of upper nanosheets. The first conductive layer is not between the gate electrode and sidewalls of the plurality of upper nanosheets.

Abstract: To improve productivity and sealing performance, the present disclosure provides a pressure vessel including a boss part including a boss extension portion that is provided in a cylindrical shape, a boss flange portion integrally extending from a lower portion of the boss extension portion, and a boss support portion integrally extending from an inner end of the boss flange portion, a fusion-coupling part insert-injected in a form surrounding an outer surface of one side of the boss support portion in the circumferential direction, and a liner part which has an accommodation space for accommodating a fluid therein, extends in a longitudinal direction, and has both open sides, and the liner part is made of the same material as the fusion-coupling part, and both inner circumferences of the liner part are in surface contact with and fusion-coupled to an outer circumference of the fusion-coupling part.

Abstract: The present invention relates to an antibody specifically binding to the peptide of SEQ ID NO: 1, and specifically, to an antibody specifically binding to an isolated peptide of SEQ ID NO: 1 or a fragment binding to the peptide specifically binding to the peptide, a polynucleotide encoding the antibody or the fragment binding to the peptide, a vector containing the polynucleotide, a cell introduced with the vector, a method of producing the antibody or the fragment binding to the peptide using the cell, an antibody or a fragment binding to the peptide produced by the method, an antiviral composition containing the antibody or the fragment binding to the peptide, a composition for preventing or treating inflammatory diseases containing the antibody or the fragment binding to the peptide, and a method of treating infectious viral diseases or inflammatory diseases using the composition.

Abstract: The present invention relates to an antibody specifically binding to the peptide of SEQ ID NO: 1, and specifically, to an antibody specifically binding to an isolated peptide of SEQ ID NO: 1 or a fragment binding to the peptide specifically binding to the peptide, a polynucleotide encoding the antibody or the fragment binding to the peptide, a vector containing the polynucleotide, a cell introduced with the vector, a method of producing the antibody or the fragment binding to the peptide using the cell, an antibody or a fragment binding to the peptide produced by the method, an antiviral composition containing the antibody or the fragment binding to the peptide, a composition for preventing or treating inflammatory diseases containing the antibody or the fragment binding to the peptide, and a method of treating infectious viral diseases or inflammatory diseases using the composition.

Abstract: A liquid crystal display separator, in which a liquid crystal display includes a liquid crystal panel and a cover glass bonded to each other by means of a resin material disposed therebetween, is disclosed. The separator includes a body unit, which is provided with a first transfer unit, positioned at a higher level, and a second transfer unit, positioned at a lower level, and which moves horizontally, a first suction unit coupled to the first transfer unit to suck a circuit board of the liquid crystal panel using a vacuum, a second suction unit coupled to the second transfer unit to suck the cover glass using a vacuum, and a separation unit for separating the liquid crystal panel and the cover glass from each other while the first or second suction unit moves horizontally on the body unit.

Abstract: A liquid crystal display separator, in which a liquid crystal display includes a liquid crystal panel and a cover glass bonded to each other by means of a resin material disposed therebetween, is disclosed. The separator includes a body unit, which is provided with a first transfer unit, positioned at a higher level, and a second transfer unit, positioned at a lower level, and which moves horizontally, a first suction unit coupled to the first transfer unit to suck a circuit board of the liquid crystal panel using a vacuum, a second suction unit coupled to the second transfer unit to suck the cover glass using a vacuum, and a separation unit for separating the liquid crystal panel and the cover glass from each other while the first or second suction unit moves horizontally on the body unit.

Abstract: A wireless local area network (WLAN) system is disclosed. The WLAN system includes a first access point (AP), and a second AP which has a same service set identifier (SSID) as that of the first AP, wherein the first AP and the second AP are configured to respectively perform a network address translation (NAT) and have a same virtual media access control (MAC) address. The WLAN system according to the present disclosure supports successful roaming between APs which belong to different networks regardless of the type of the wireless terminal.

Abstract: Provided are a method and system for testing a semiconductor memory device using an internal clock signal of the semiconductor memory device as a data strobe signal. The internally-generated data strobe signal may be delayed to synchronize with test data. Because a test device need not supply the data strobe signal, the number of semiconductor memory modules that can be simultaneously tested can be increased, and an average test time for a unit memory module can be decreased.

Abstract: An apparatus for correcting a duty cycle of an input clock signal to generate a digitally corrected clock signal includes a duty cycle detector, an analog duty cycle correcting unit, and a digital duty cycle correcting unit. The duty cycle detector generates a duty cycle signal indicating a respective duty cycle of the digitally corrected clock signal. The analog duty cycle correcting unit adjusts a current flowing through a node to adjust the respective duty cycle of the input clock signal for generating an analog corrected clock signal at the node. The digital duty cycle correcting unit adjusts the respective duty cycle of the analog corrected clock signal according to the duty cycle signal for generating the digitally corrected clock signal.

Abstract: A content addressable merged queue (camQ) architecture for switching data. The camQ architecture comprises a first array of priority cells for indicating a priority of a plurality of cells and a second array of destination cells for indicating a destination of the plurality of cells. A priority selector is operable to select a portion of said plurality of cells according to a priority selection. A grant generator is operable to grant at least one connection request associated with cells of the portion.

Abstract: Provided are a method and system for testing a semiconductor memory device using an internal clock signal of the semiconductor memory device as a data strobe signal. The internally-generated data strobe signal may be delayed to synchronize with test data. Because a test device need not supply the data strobe signal, the number of semiconductor memory modules that can be simultaneously tested can be increased, and an average test time for a unit memory module can be decreased.

Abstract: A content addressable merged queue (camQ) architecture for high-speed switch fabrics reduces the memory requirement for crossbar switch input and output queues using memory cells and age tag comparators. CamQ emulates VOQ FIFO for each supporting priority, eliminating HOL blocking. Multiple QoS levels are supported cost effectively at higher traffic bandwidth limits. Content addressable memory (CAM) cells store payload destinations, which can be addressed by cell priorities. Once a priority for QoS is decided, all the cells with the selected priority in the payload can make connection requests to destination ports directly through the CAM structure. An age tag is assigned to incoming cells and fast age tag comparators provide FCFS features by selecting the oldest cell. Small memory sizes prevent the bottlenecking in ingress and egress queues. A CIOQ crossbar has a fast switching speed, emulating a FIFO output queue switch. Age and priority are interleaved to schedule switching.

Abstract: A delay locked loop includes a variable delay unit, a phase inversion unit, a delay selecting unit, a delay control unit and an inversion control unit. The variable delay unit delays a reference clock signal based on phase difference between a first feedback clock signal and a reference clock signal, outputted from the delay control unit. The phase inversion unit selectively inverts the delayed clock signal in response to a phase inversion control signal and generates a reproduction clock signal. The delay selecting unit selectively delays the first feedback clock signal corresponding to the reproduction clock signal in response to an inversion control termination signal to generate a second feedback clock signal. The inversion control unit generates the phase inversion control signal when the phase difference between the delayed feedback clock signal and the reference clock signal is larger than a half clock-cycle, and generates the inversion control termination signal.

Abstract: The circuit of the present invention prevents a multi-locking phenomenon, reduces power consumption and provides an accurately locked internal clock signal. A delay unit sequentially delays an external clock signal through a plurality of unit delay terminals. A sampling and computation unit maintains the levels of signals from the unit delay terminals connected after a predetermined unit delay terminal, in which a locking phenomenon occurs, to a predetermined level when a delay clock signal among a plurality of delay clock signals from the unit delay terminals is locked. An output unit outputs a delay clock signal locked to an external clock signal in accordance with an output from the sampling and computation unit.

Abstract: An improved clock signal modeling circuit capable of more quickly generating an internal clock signal in an external clock signal without using a phase locked loop and a delay locked loop, which includes a delay unit for receiving an external clock signal and for outputting a delay clock sinal; a sampling unit for receiving the delay clock signal and for sampling in accordance with an external clock signal; a comparing unit for receiving the output of the sampling unit and for sequentially comparing the output; and an output unit for receiving the delay clock signal outputted from the delay unit and for outputting an internal clock signal in accordance with an output signal of the comparing unit and an externally applied switching signal.

Abstract: An improved clock signal modeling circuit capable of more quickly generating an internal clock signal in an external clock signal without using a phase locked loop and a delay locked loop, which includes a delay unit for receiving an external clock signal and for outputting a delay clock signal; a sampling unit for receiving the delay clock signal and for sampling in accordance with an external clock signal; a comparing unit for receiving the output of the sampling unit and for sequentially comparing the output; and an output unit for receiving the delay clock signal outputted from the delay unit and for outputting an internal clock signal in accordance with an output signal of the comparing unit and an externally applied switching signal.