Abstract: A method for manufacturing a memory includes the following steps. An insulating layer, a polysilicon layer and a mask layer are formed on a substrate in sequence. Next, the mask layer is etched to expose portions of the polysilicon layer, and to define a first patterned region, a second patterned region and a third patterned region located between the first and second patterned regions. The exposed portions of the polysilicon layer are located in the first and second patterned regions. The portion of the polysilicon layer exposed in the second patterned region is then etched. An ion implanting process is performed to implant ions into the substrate so as to form a first doped region in the second patterned region. The substrate is oxidized to form a first silicon oxide region in the first patterned region. The mask layer is then removed, and the polysilicon layer is etched to form a gate with using the first silicon oxide region as a mask.

Abstract: A method for manufacturing a memory includes the following steps. An insulating layer, a polysilicon layer and a mask layer are formed on a substrate in sequence. Next, the mask layer is etched to expose portions of the polysilicon layer, and to define a first patterned region, a second patterned region and a third patterned region located between the first and second patterned regions. The exposed portions of the polysilicon layer are located in the first and second patterned regions. The portion of the polysilicon layer exposed in the second patterned region is then etched. An ion implanting process is performed to implant ions into the substrate so as to form a first doped region in the second patterned region. The substrate is oxidized to form a first silicon oxide region in the first patterned region. The mask layer is then removed, and the polysilicon layer is etched to form a gate with using the first silicon oxide region as a mask.

Abstract: A fabrication method for a high voltage electrically erasable read only memory is described, wherein a substrate comprising a memory device region and a peripheral high voltage circuit region is provided. A floating gate is formed on the substrate in the device region, while a gate electrode is formed on the substrate in the peripheral circuit region. Thereafter, an oxide/nitride/oxide layer is formed on the substrate, wherein the oxide/nitride/oxide layer is formed by stacking from bottom to top a first oxide layer, a nitride layer and a second oxide layer. The second oxide layer in the peripheral high voltage circuit region is then removed, followed by removing the nitride layer in the peripheral high voltage circuit region. An oxidation on the second oxide layer and a double diffused drain implantation are conducted to form a bird's beak structure at the bottom corner of the gate electrode and to form a double diffused drain structure in the substrate on both sides of the gate electrode.

Abstract: A method for fabricating a non-volatile memory cell for a substrate includes the following steps: forming an isolation structure to define an active region on the substrate; forming a channel oxide layer on the active region; forming a conducting layer and a silicon nitride layer over the substrate; defining the polysilicon layer and the silicon nitride layer to form a floating gate on the active region and to form an opening exposing a portion of the isolation structure; conformally forming an etching protection layer which extends from the isolation structure inside the opening up to the silicon nitride layer; forming an oxide layer over the substrate; planarizing the oxide layer to the surface of the silicon nitride layer so that the remainder of the oxide layer is left within the opening; removing the silicon nitride layer; forming conducting spacers on the sidewalls of the remainder of the oxide layer; removing the remainder of the TEOS oxide layer; conformally forming an ONO layer; forming a controlling

Abstract: This invention provides a multi-layer multi-phase phase shifting photomask and a method for fabricating the same. The photomask of this invention uses a number of phase shifting layers each layer providing less than 180°optical phase shift to provide a total optical phase shift of 180°. The multi-layer multi-phase phase shifting photomask provides a gradual transition form no phase shift to 180° phase shift at pattern edges thereby improving image quality. The patterns in the layers of phase shifting material are formed using non critical etching steps. The thickness of the phase shifting layers is controlled by the deposition of the layers of phase shifting material which is relatively easy to control.

Abstract: An anti-reflective reticle and a method by which the anti-reflective reticle is formed. Formed upon a first surface of a transparent substrate is a patterned metal layer. Formed upon the first surface of the transparent substrate including the patterned metal layer is a two-layer dielectric stack. The two layer dielectric stack has a first dielectric layer which is closer to the transparent substrate and a second dielectric layer which is formed directly upon the first dielectric layer. The first dielectric layer has an index of refraction greater than the index of refraction of the transparent substrate or the second dielectric layer. The second dielectric layer has a thickness of about one-quarter the wavelength of reflected light desired to be attenuated or eliminated from the surface of the reticle.

Abstract: This invention relates to a method for protecting regions of a spin-on-glass(SOG) layer, which covers usable semiconductor dice, from dissolution damage during an etch step which removes SOG along the wafer edge. The endangered dice have portions which lie in the area affected by the edge rinse. Instead of performing the edge etching step immediately after the deposition of the SOG, the endangered dice are first selectively partially cured by exposure to ultraviolet radiation. This makes the SOG over these dice resistant to the SOG solvent used for the edge rinse. Up to ten percent of the total usable dice on the wafer can be salvaged by the method of this invention.

Abstract: An anti-reflective reticle and a method by which the anti-reflective reticle is formed. Formed upon a first surface of a transparent substrate is a patterned metal layer. Formed upon at least one of: (1) the first surface of the transparent substrate including the patterned metal layer; or (2) the surface of the transparent substrate opposite the patterned metal layer is a two-layer dielectric stack. The two layer dielectric stack has a first dielectric layer which is closer to the transparent substrate and a second dielectric layer which is formed directly upon the first dielectric layer. The first dielectric layer has an index of refraction greater than the index of refraction of the transparent substrate or the second dielectric layer. The second dielectric layer has a thickness of about one-quarter the wavelength of reflected light desired to be attenuated or eliminated from the surface of the reticle.

Abstract: A test structure is described which indicates the occurrence of plasma damage resulting from back-end-of-line processing of integrated circuits. The structure consists of a MOSFET which is surrounded by a conductive shield grounded to the substrate silicon along its base perimeter. The walls of the shield are formed from the sundry levels of conductive layers applied during the integrated circuit interconnection metallization beginning with contact metallurgy which is connected to a diffusion within the substrate. This diffusion is formed within a trench in field oxide surrounding the MOSFET and is of the same conductive type as the substrate material. The top conductive plate of the test structure is formed from a selected metallization layer of the integrated circuit. By forming test structures with top conductive plates formed from two different metallization levels, the plasma damage incurred during the intervening processing steps can be uniquely determined.

Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate is provided. An N+ source layer is formed on the surface of the semiconductor substrate. A dielectric layer is formed on the surface of the source layer. The dielectric layer is patterned and etched forming a dielectric layer pattern with openings therein, a silicon epitaxial layer in the openings in the dielectric layer pattern. An N+ drain layer is formed on the surface of the silicon epitaxial layer. A second dielectric layer is formed on the surface of the device including the N+ drain layer. A conductor layer is formed and patterned containing silicon over the second dielectric layer. An N+ implant mask with an N+ opening over a region of the epitaxial layer is formed (source) and ion implanting through that N+ opening into the N+ implant mask in that region. A code implant mask over the conductor layer is formed and ions are implanted through the code implant mask into the device.

Abstract: A method for plasma hardening a patterned photoresist layer. There is first provided a semiconductor substrate which has formed upon its surface a patterned photoresist layer. The patterned photoresist layer is then exposed to a hydrogen containing plasma for a time sufficient to harden the patterned photoresist layer against a Reactive Ion Etch (RIE) etch plasma to which the patterned photoresist layer is later exposed. A blanket layer residing beneath the plasma hardened photoresist layer may then be patterned through the Reactive Ion Etch (RIE) etch plasma without softening, erosion and/or consumption of the plasma hardened patterned photoresist layer.

Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate is provided. An N+ source layer is formed on the surface of the semiconductor substrate. A dielectric layer is formed on the surface of the source layer. The dielectric layer is patterned and etched forming a dielectric layer pattern with openings therein, a silicon epitaxial layer in the openings in the dielectric layer pattern. An N+ drain layer is formed on the surface of the silicon epitaxial layer. A second dielectric layer is formed on the surface of the device including the N+ drain layer. A conductor layer is formed and patterned containing silicon over the second dielectric layer. An N+ implant mask with an N+ opening over a region of the epitaxial layer is formed (source) and ion implanting through that N+ opening into the N+ implant mask in that region. A code implant mask over the conductor layer is formed and ions are implanted through the code implant mask into the device.