Abstract: Disclosed are a double data rate synchronous dynamic random access memory module and a configuring method thereof. The DDR SDRAM module in accordance with an embodiment of the present invention includes: a plurality of memory chips; and a serial transceiver portion configured to serially receive first serial data including a control signal and data transferred from outside for the plurality of memory chips and to provide the control signal and the data included in the serially received first serial data to the plurality of memory chips.

Abstract: Disclosed herein are a data transmission apparatus, a data reception apparatus, and a data transmission method. The data transmission apparatus, the data reception apparatus, and the data transmission method are capable of simplifying the circuit structure of a decoder because an assumption of the time related to a request signal and a data signal is not necessary and an additional logic for generating a clock signal for the decoder is not necessary by using a Finite State Machine (FSM) logic without storing a state via a delay device.

Abstract: A ramp waveform generating apparatus generates a reference waveform by using an input signal and generates a driving control signal for turning on and off a switch having a first terminal connected to a load and a second terminal connected to a power supply by comparing the voltage of the reference waveform with the voltage of the load. While the switch is repetitively turned on and off in accordance with the driving control signal, a ramp waveform may be generated.

Abstract: Disclosed is a radiographic apparatus including a detachable manipulation panel which includes a capturing device to generate X-rays and to irradiate the X-rays to a subject so as to capture the subject, a controller connected to the capturing device to control the capturing device, and a manipulation device mounted to the capturing device to allow an inspector to input commands to control the capturing device, wherein the manipulation device is detachably mounted to the capturing device and, in a state in which the manipulation device is separated from the capturing device, is connected to the controller using a wireless interface to control the capturing device.

Abstract: Disclosed herein is an apparatus for simulating an asynchronous circuit in an FPGA. The apparatus includes a plurality of function execution units, a plurality of delay circuits, and a control unit. The function execution units are set for respective unit functions included in the asynchronous circuit, and are configured to perform the unit functions. The delay circuits are provided for the respective function execution units using a look-up table in the FPGA, and are configured to output delayed input signals by delaying input signals by respective preset delay times. The control unit transmits the input signals to the delay circuits and the function execution units, and receives the delayed input signals from the respective delay circuits.

Abstract: Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.

Abstract: Disclosed are an asynchronous pipeline system, a stage, and a data transfer mechanism. The asynchronous pipeline system having a plurality of stages based on a 4-phase protocol, includes: a first stage among the plurality of stages; and a second stage among the plurality of stages connected next to the first stage, wherein the first stage transmits and the second receives bundled data and control data through an always bundled data channel and on-demand data through an on-demand data channel according to need of the second stage.

Abstract: Provided is a bus signal encoding/decoding method and apparatus. The bus signal encoding method includes receiving a bus signal, XOR-operating all but the first byte sequence of the bus signal in a bitwise manner, inverting the even-numbered byte sequences of the XOR-operated bus signal in a bitwise manner, and serializing the inverted bus signal.

Abstract: A radiography apparatus and a control method thereof are provided. With provision of a user centered input unit, automated horizontal and rotational movement of a detector may be performed, enabling automated full-body radiography.

Abstract: A ramp waveform generating apparatus generates a reference waveform by using an input signal and generates a driving control signal for turning on and off a switch having a first terminal connected to a load and a second terminal connected to a power supply by comparing the voltage of the reference waveform with the voltage of the load. While the switch is repetitively turned on and off in accordance with the driving control signal, a ramp waveform may be generated.

Abstract: Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated.

Abstract: Provided is a bus signal encoding/decoding method and apparatus. The bus signal encoding method includes receiving a bus signal, XOR-operating all but the first byte sequence of the bus signal in a bitwise manner, inverting the even-numbered byte sequences of the XOR-operated bus signal in a bitwise manner, and serializing the inverted bus signal.

Abstract: Provided are a microprocessor suitable for constructing a multi-processor system and a method for controlling the reset and processor ID of the microprocessor. The microprocessor includes decoder receiving a reset ID having a predetermined binary value and a reset signal and decoding the reset ID, an ID generator receiving the decoding result of the decoder and generating at least one microprocessor ID and a reset ID of a microprocessor serially connected to the microprocessor, and a reset vector unit selecting a reset vector according to the decoding result of the decoder. The multi-processor system is constructed such that independent microprocessors of the system respectively generate their own reset vectors and processor IDs when a reset signal is input to the multi-processor system to initialize it. Thus, all the microprocessors of the system can be simultaneously started up when the reset signal is disabled.

Abstract: Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.

Abstract: Provided are a high-performance wrapper circuit for a globally asynchronous locally synchronous (GALS) system and a synchronization method using the same, which are capable of solving a synchronization problem caused when data are transmitted between locally synchronous modules employing different clocks, and a method for operating the wrapper circuit. The GALS system includes a clock generator for supplying an operation clock to a locally synchronous module, a sender port for transmitting data to the outside according to a data transmission request signal output from the locally synchronous module, and generating a first clock stop signal for stopping an operation of the clock generator, and a receiver port for receiving data from the outside, and generating a second clock stop signal for stopping the operation of the clock generator.

Abstract: Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated.

Abstract: The present invention relates to an imaging device having a touch screen as a user interface and a method of changing attributes of a soft button provided on the touch screen. Each of the attributes has an attribute name and a plurality of attribute values. The method includes: receiving a request for designating a soft button and changing attributes of the designated soft button through the touch screen; providing a window displaying attribute names associated with the designated soft button on the touch screen in response to the request; receiving a selection instruction to select one of the attribute names on the window; receiving change information for changing an attribute value corresponding to the selected attribute name; and changing the attribute value of the designated soft button based on the change information.

Abstract: A shredded parallel stacked inductor is provided. The shredded parallel stacked inductor includes a substrate, an oxide film formed on the substrate, metallic layers spirally formed within the oxide film, and vias formed in regions of the metallic layers to join the metallic layers in parallel, thus forming a spiral cavity in a center part of the metallic layers.

Abstract: A shredded parallel stacked inductor is provided. The shredded parallel stacked inductor includes a substrate, an oxide film formed on the substrate, metallic layers spirally formed within the oxide film, and vias formed in regions of the metallic layers to join the metallic layers in parallel, thus forming a spiral cavity in a center part of the metallic layers.

Abstract: A device for effectively and economically receiving a packet by eliminating temporary memory and a memory controller. The apparatus includes an inspection logic circuit for inspecting data units as soon as they arrive in order to find an error included in the packet and generating control signals according to a result of inspecting a data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units have arrived; and FIFO memories for receiving the data unit, storing the data unit in a corresponding one of FIFO memories and either deleting or completing storing data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the device by eliminating a temporary memory and a memory controller for the temporary memory and can also reduce processing time.