Abstract: A computer system having switchable 3.3 volt or 5 volt interface bus. The computer system includes a microprocessor and multiple peripheral integrated circuits. The microprocessor and other peripheral integrated circuits are coupled to the interface bus through groups of buffers on the integrated circuits. These buffers operate at the voltage level of the interface bus and include voltage translation circuitry for translating interface bus signals to voltage level at which the core logic of the microprocessor and other peripheral chips operate.

Abstract: A computer architecture which provides for the dynamic configuration of peripheral interrupts. A global router is implemented for mapping interrupts received over a multiple-line shared interrupt bus to correspond to system standard IRQ interrupt signals for a programable interrupt controller (PIC). The global router may configure interrupts to be both level sensitive and edge-triggered interrupts as well as being sharable among multiple devices. The global router further provides its interrupts to a shared interrupt bus which may receive other system interrupts for propagation to the computer system's PIC. The global router provides a centrally located motherboard resource that provides a totally flexible interrupt configuration scheme.

Abstract: A transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of a microprocessor CPU chip. Upon assertion of this interrupt, the CPU begins program execution in a dedicated RAM area that is inaccessible both to the operating system and all application programs. A set of instructions, which may be unique to the system in which the CPU chip is installed, services the interrupt. Typically, the state of the CPU and associated components in the system immediately prior to assertion of the interrupt will be saved into the dedicated RAM area by the interrupt service routine. Recovery from the interrupt is accomplished upon recognition of an external event that invokes a RESUME instruction causing the CPU and associated components to be restored to exactly the same state that existed prior to the interrupt and in a manner entirely transparent to any program executing at the time of the interrupt.

Abstract: A transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of a microprocessor CPU chip. Upon assertion of this interrupt, the CPU begins program execution in a dedicated RAM area that is inaccessible both to the operating system and all application programs. A set of instructions, which may be unique to the system in which the CPU chip is installed, services the interrupt. Typically, the state of the CPU and associated components in the system immediately prior to assertion of the interrupt will be saved into the dedicated RAM area by the interrupt service routine. Recovery from the interrupt is accomplished upon recognition of an external event that invokes a RESUME instruction causing the CPU and associated components to be restored to exactly the same state that existed prior to the interrupt and in a manner entirely transparent to any program executing at the time of the interrupt.