Patents by Inventor Sung Sam Lee
Sung Sam Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240072811Abstract: A clock and data recovery device includes an equalizer that compensates for channel loss of input data, a phase detector that compares a data output from the equalizer with a clock fed back and outputs an up signal and a down signal, a charge pump that operates according to the up signal and the down signal and outputs a control signal, a loop filter that removes high-frequency components included in the control signal, a voltage controlled oscillator that changes a frequency of the clock and outputs a clock with changed frequency, and a data phase adjuster that synchronizes the clock output from the voltage controlled oscillator and the data output from the equalizer by adjusting a phase of the data output from the equalizer by receiving the up signal and the down signal output from the phase detector.Type: ApplicationFiled: June 30, 2023Publication date: February 29, 2024Applicants: SILICON MITUS, INC., Hangzhou Silicon-Magic Semiconductor Technology Co., Ltd.Inventors: Young Jae Chang, Sung Ryong Lee, Jae Sam Shim
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Patent number: 10199379Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.Type: GrantFiled: December 7, 2017Date of Patent: February 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee
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Patent number: 10032780Abstract: A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of dummy contact plugs each electrically connected between two adjacent dummy wirings of the plurality of dummy wiring of the plurality of dummy wirings. No dummy wiring of the plurality of dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate.Type: GrantFiled: April 27, 2016Date of Patent: July 24, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Hee Cho, Satoru Yamada, Sung-Sam Lee, Jung-Bun Lee
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Publication number: 20180108662Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.Type: ApplicationFiled: December 7, 2017Publication date: April 19, 2018Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee
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Patent number: 9853031Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.Type: GrantFiled: February 15, 2017Date of Patent: December 26, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee
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Publication number: 20170005100Abstract: A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of dummy contact plugs each electrically connected between two adjacent dummy wirings of the plurality of dummy wiring of the plurality of dummy wirings. No dummy wiring of the plurality of dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate.Type: ApplicationFiled: April 27, 2016Publication date: January 5, 2017Inventors: Min Hee CHO, Satoru YAMADA, Sung-Sam LEE, Jung-Bun LEE
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Patent number: 9390784Abstract: A semiconductor memory device includes: a memory unit including a first memory sub region including a first memory cell and a second memory sub region including a second memory cell; a temperature information obtaining unit that obtains temperature information; a temperature estimation unit that estimates a first temperature of the first memory sub region and a second temperature of the second memory sub region based on the temperature information; a first sub region control unit that controls the first memory sub region based on the first temperature; and a second sub region control unit that controls the second memory sub region based on the second temperature.Type: GrantFiled: May 29, 2014Date of Patent: July 12, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-hee Cho, Satoru Yamada, Sang-ho Shin, Sung-sam Lee
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Patent number: 9337105Abstract: A method for fabricating a semiconductor device is provided. The method for fabricating a semiconductor device includes forming transistors on a semiconductor substrate, each of the transistors having a gate structure and source/drain regions, forming an oxide film on the transistors, forming a mask film pattern on the oxide film, the mask film pattern comprising a first pattern having a first width and a second pattern having a second width different from the first width, removing a part of the oxide film using the mask film pattern to form first and second trenches, filling the first and second trenches with a nitride film, removing the rest part of the oxide film to form third and fourth trenches, and forming conductive contacts by filling the third and fourth trenches. A top width of each of the third trenches is equal to the first width, and a top width of each of the fourth trenches is equal to the second width.Type: GrantFiled: June 8, 2015Date of Patent: May 10, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Bum Kwon, Sung-Sam Lee
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Publication number: 20140369110Abstract: A semiconductor memory device includes: a memory unit including a first memory sub region including a first memory cell and a second memory sub region including a second memory cell; a temperature information obtaining unit that obtains temperature information; a temperature estimation unit that estimates a first temperature of the first memory sub region and a second temperature of the second memory sub region based on the temperature information; a first sub region control unit that controls the first memory sub region based on the first temperature; and a second sub region control unit that controls the second memory sub region based on the second temperature.Type: ApplicationFiled: May 29, 2014Publication date: December 18, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-hee CHO, Satoru YAMADA, Sang-ho SHIN, Sung-sam LEE
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Patent number: 8426274Abstract: Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.Type: GrantFiled: August 23, 2010Date of Patent: April 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Ho Yoon, Kyoung-Sub Shin, Sung-Sam Lee, Kung-Hyon Nam, Hong Cho, Joon-Seok Moon
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Publication number: 20130043519Abstract: A device includes a semiconductor substrate and a gate insulation film lining a trench in an active region of the substrate. A gate electrode pattern is recessed in the trench on the gate insulation film and has an upper surface that has a nonuniform height. A dielectric pattern may be disposed on the gate electrode pattern in the trench.Type: ApplicationFiled: August 20, 2012Publication date: February 21, 2013Inventors: Joon-seok Moon, Jae-rok Kahng, Jin-woo Lee, Sung-sam Lee, Dong-soo Woo, Kyoung-ho Jung, Jung-kyu Jung
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Patent number: 8329539Abstract: In a semiconductor device having a recessed gate electrode and a method of fabricating the same, a channel trench is formed in a semiconductor substrate by etching the semiconductor substrate. A first semiconductor layer is formed on the semiconductor substrate that fills the channel trench. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer having a lower impurity concentration than the first semiconductor layer.Type: GrantFiled: May 8, 2006Date of Patent: December 11, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Won Ha, Kong-Soo Lee, Sung-Sam Lee, Sang-Hyun Lee, Min-Young Shim
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Patent number: 8133786Abstract: A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.Type: GrantFiled: January 28, 2011Date of Patent: March 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Sam Lee, Min-Hee Cho
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Patent number: 8035136Abstract: In a semiconductor device and a method of manufacturing the same, a substrate is defined into active and non-active regions by a device isolation layer and a recessed portion is formed on the active region. A gate electrode includes a gate insulation layer on an inner sidewall and a bottom of the recessed portion, a lower electrode on the gate insulation layer and an inner spacer on the lower electrode in the recessed portion, and an upper electrode that is positioned on the inner spacer and connected to the lower electrode. Source and drain impurity regions are formed at surface portions of the active region of the substrate adjacent to the upper electrode. Accordingly, the source and drain impurity regions are electrically insulated by the inner spacer in the recessed portion of the substrate like a bridge, to thereby sufficiently prevent gate-induced drain leakage (GIDL) at the gate electrode.Type: GrantFiled: July 23, 2009Date of Patent: October 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Sam Lee, Joon-Seok Moon, Young-Ju Choi
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Publication number: 20110183482Abstract: A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.Type: ApplicationFiled: January 28, 2011Publication date: July 28, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Sam LEE, Min-Hee CHO
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Patent number: 7902597Abstract: A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.Type: GrantFiled: February 5, 2008Date of Patent: March 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Sam Lee, Min-Hee Cho
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Publication number: 20110053327Abstract: Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.Type: ApplicationFiled: August 23, 2010Publication date: March 3, 2011Inventors: Jun-Ho YOON, Kyoung-Sub Shin, Sung-Sam Lee, Kung-Hyon Nam, Hong Cho, Joon-Seok Moon
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Publication number: 20100019302Abstract: In a semiconductor device and a method of manufacturing the same, a substrate is defined into active and non-active regions by a device isolation layer and a recessed portion is formed on the active region. A gate electrode includes a gate insulation layer on an inner sidewall and a bottom of the recessed portion, a lower electrode on the gate insulation layer and an inner spacer on the lower electrode in the recessed portion, and an upper electrode that is positioned on the inner spacer and connected to the lower electrode. Source and drain impurity regions are formed at surface portions of the active region of the substrate adjacent to the upper electrode. Accordingly, the source and drain impurity regions are electrically insulated by the inner spacer in the recessed portion of the substrate like a bridge, to thereby sufficiently prevent gate-induced drain leakage (GIDL) at the gate electrode.Type: ApplicationFiled: July 23, 2009Publication date: January 28, 2010Inventors: Sung-Sam Lee, Joon-Seok Moon, Young-Ju Choi
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Patent number: 7622778Abstract: In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower trench is in communication with the upper trench. Since the upper trench has a sidewall tapered with a positive slope, a good gap filling property can be obtained when filling the upper trench with an insulating layer. By forming a void in the lower trench, a dielectric constant at the bottom of the isolation layer is lower than a dielectric constant at an oxide layer, thereby improving the isolation property. The isolation layer includes a first insulating layer formed inside only the upper trench and covering an inner wall of the upper trench in the form of a spacer.Type: GrantFiled: May 12, 2006Date of Patent: November 24, 2009Assignee: Samsung Electronic Co., Ltd.Inventors: Sung-Sam Lee, Gyo-Young Jin, Yun-Gi Kim
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Patent number: 7553748Abstract: According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.Type: GrantFiled: August 10, 2006Date of Patent: June 30, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Ho Jang, Sang-Ho Song, Sung-Sam Lee, Min-Sung Kang, Won-Tae Park, Min-Young Shim