Patents by Inventor Sung-Sang Lim

Sung-Sang Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10573761
    Abstract: A pressure sensor includes a semiconductor layer, a gate electrode, a gate insulating layer, and a source electrode, and may be incorporated as a switching transistor in a display device. The gate electrode is configured to overlap the semiconductor layer. The gate insulating layer is disposed between the semiconductor layer and the gate electrode and includes a first insulating layer disposed on a surface of the semiconductor layer that faces the gate electrode and a second insulating layer comprising an elastic material disposed at least between the first insulating layer and the gate electrode. The source electrode and a drain electrode respectively coupled to spaced portions of the semiconductor layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: February 25, 2020
    Assignees: Samsung Display Co., Ltd., UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Jae Ik Lim, Won Sang Park, Hye Yong Chu, Jang-Ung Park, Sung-Ho Shin, Sangyoon Jin, Seiho Choi
  • Patent number: 10433102
    Abstract: A position associated information providing method, implemented by an electronic device supporting the same, includes identifying a condition of position information set to an application running or execution-requested, obtaining position information corresponding to the identified condition of the position information, and providing the obtained position information to the application.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: October 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye Jeong Kim, Chae Man Lim, Sung Rae Cho, Yun Sang Park, Moon Gyo Bae
  • Publication number: 20190189615
    Abstract: A semiconductor device includes a substrate, a conductive pattern on the substrate, a lower electrode electrically connected to the conductive pattern, a dielectric layer covering a surface of the lower electrode, a first upper electrode on the dielectric layer, a diffusion barrier on an upper surface of the first upper electrode, and a second upper electrode covering the diffusion barrier, the second upper electrode including a different material from that of the first upper electrode.
    Type: Application
    Filed: February 21, 2019
    Publication date: June 20, 2019
    Inventors: Hoon-Sang CHOI, Hyeok-Jin JEONG, Jung-Kun LIM, Young-Mo TAK, Sung-Kil HAN
  • Patent number: 10305446
    Abstract: A piezoelectric oscillator, and method of making the same, includes an oscillation substrate comprising an oscillating part and a surrounding part, wherein the surrounding part is thinner than the oscillating part, and oscillating electrodes disposed on an upper surface and a lower surface of the oscillating part. The oscillation substrate is configured according to H=400.59×S+1.75±1.5, wherein H=100×(T2/T1) and S=T2/(L1?L2), wherein L1 represents an entire length of the oscillation substrate, L2 represents a length of the oscillating part, T1 represents a thickness of the oscillating part, and T2 represents a step height between the oscillating part and the surrounding part.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: May 28, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Sang Lee, Ho Phil Jung, Sung Wook Kim, Tae Joon Park, In Young Kang, Dong Joon Oh, Je Hong Kyoung, Kyo Yeol Lee, Jong Pil Lee, Seung Mo Lim
  • Patent number: 9094030
    Abstract: An analog to digital converter includes a digital to analog converting circuit, a comparator and a signal processing circuit. The digital to analog converting circuit samples and holds an analog input signal, and converts digital output data to an analog signal to generate a hold voltage signal. The comparator compares the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: July 28, 2015
    Assignee: SAMSUNG ELECTRONICS CORPORATION
    Inventors: Jung-Ho Lee, Sung-Sang Lim, Yong-Woo Kim, Michael Choi
  • Publication number: 20130335245
    Abstract: An analog to digital converter includes a digital to analog converting circuit, a comparator and a signal processing circuit. The digital to analog converting circuit samples and holds an analog input signal, and converts digital output data to an analog signal to generate a hold voltage signal. The comparator compares the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data.
    Type: Application
    Filed: July 3, 2013
    Publication date: December 19, 2013
    Inventors: Jung-Ho LEE, Sung-Sang Lim, Yong-Woo Kim, Michael Choi
  • Patent number: 8508399
    Abstract: An analog to digital converter includes a digital to analog converting circuit, a comparator and a signal processing circuit. The digital to analog converting circuit samples and holds an analog input signal, and converts digital output data to an analog signal to generate a hold voltage signal. The comparator compares the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: August 13, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Lee, Sung-Sang Lim, Yong-Woo Kim, Michael Choi
  • Publication number: 20120007758
    Abstract: An analog to digital converter includes a digital to analog converting circuit, a comparator and a signal processing circuit. The digital to analog converting circuit samples and holds an analog input signal, and converts digital output data to an analog signal to generate a hold voltage signal. The comparator compares the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data.
    Type: Application
    Filed: June 20, 2011
    Publication date: January 12, 2012
    Inventors: Jung-Ho Lee, Sung-Sang Lim, Yong-Woo Kim, Michael Choi
  • Patent number: 7385427
    Abstract: An electronic device, such as a sample-and-hold circuit, includes a field effect transistor (FET), a capacitor, and a voltage offset circuit. The FET is configured to receive a signal at a first terminal thereof and selectively provide the signal to a second terminal thereof responsive to a switching signal at a gate terminal thereof. The capacitor is electrically connected to the second terminal of the FET. The voltage offset circuit is electrically connected to the first terminal and the gate terminal of the FET. The voltage offset circuit is configured to maintain a substantially constant voltage differential between the first terminal and the gate terminal of the FET while the signal is provided to the second terminal of the FET and substantially independent of a voltage level of an input signal. Related methods of operation are also discussed.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: June 10, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sung-Sang Lim
  • Publication number: 20070013417
    Abstract: An electronic device, such as a sample-and-hold circuit, includes a field effect transistor (FET), a capacitor, and a voltage offset circuit. The FET is configured to receive a signal at a first terminal thereof and selectively provide the signal to a second terminal thereof responsive to a switching signal at a gate terminal thereof. The capacitor is electrically connected to the second terminal of the FET. The voltage offset circuit is electrically connected to the first terminal and the gate terminal of the FET. The voltage offset circuit is configured to maintain a substantially constant voltage differential between the first terminal and the gate terminal of the FET while the signal is provided to the second terminal of the FET and substantially independent of a voltage level of an input signal. Related methods of operation are also discussed.
    Type: Application
    Filed: May 31, 2006
    Publication date: January 18, 2007
    Inventor: Sung-Sang Lim