Abstract: A semiconductor device includes a gate trench formed in a substrate, a gate dielectric layer formed along profile of sidewalls and a bottom surface of the gate trench, first and second gate electrodes that are stacked over the gate dielectric layer to gap-fill a portion of the gate trench, a dipole inducing portion positioned between the second gate electrode and the gate dielectric layer and including a dipole bond and a non-dipole bond, and a capping layer suitable for gap-filling a remaining portion of the gate trench over the dipole inducing portion and the second gate electrode.

Abstract: A power module includes an upper substrate and a lower substrate, an upper chip, a lower chip, and a circuit board disposed across a space between the upper substrate and the lower chip and a space between the lower substrate and the upper chip so that the upper substrate and the lower substrate are vertically spaced from each other. The circuit board electrically connects the upper chip to the lower substrate while electrically connecting the lower chip to the upper substrate.

Abstract: A light detection and ranging (lidar) device includes: a lower base; an upper base; a laser emitting unit for emitting a laser in a form of a point light source; a nodding mirror for transforming the laser in the form of the point light source to a line beam pattern which is perpendicular to the lower base, wherein the nodding mirror reflects the laser emitted from the laser emitting unit; a polygonal mirror for transforming the line beam pattern to a plane beam pattern and receiving a laser reflected from an object; and a sensor unit for receiving the laser reflected from the object via the polygonal mirror.

Abstract: A power module for a vehicle, includes: a first substrate including a first metal circuit disposed on a 1-1st surface, and a first spacer extending from the first metal circuit in a first direction; a second substrate spaced from and facing the first substrate in a second direction, and including a second metal circuit disposed on a 2-1st surface facing the 1-1st surface, and a second spacer extending from the second metal circuit in the second direction; and a semiconductor chip disposed between the first substrate and the second substrate, the first spacer and the second spacer extending toward each other.

Abstract: Provided are a silicon nitride film etching composition, a method of etching a silicon nitride film using the same, and a manufacturing method of a semiconductor device. Specifically, a silicon nitride film may be stably etched with a high selection ratio relative to a silicon oxide film, and when the composition is applied to an etching process at a high temperature and a semiconductor manufacturing process, not only no precipitate occurs but also anomalous growth in which the thickness of the silicon oxide film is rather increased does not occur, thereby minimizing defects and reliability reduction.

Abstract: A semiconductor device includes a gate stack structure including insulating patterns and conductive patterns which are alternately stacked, a first separation structure penetrating the gate stack structure, a second separation structure penetrating the gate stack structure and being adjacent to the first separation structure, first and second memory channel structures penetrating the gate stack structure and disposed between the first separation structure and the second separation structure, a first bit line overlapping with the first and second memory channel structures and electrically connected to the first memory channel structure, and a second bit line overlapping with the first and second memory channel structures and the first bit line and electrically connected to the second memory channel structure.

Abstract: A semiconductor memory device includes a gate stack structure including insulating layers, a lower selection line and word lines, the word lines including a first word line adjacent to the lower selection line and a second word line on the first word line, a memory channel structure penetrating the gate stack structure, a plurality of first contact plugs electrically connected to the first word line, a plurality of second contact plugs electrically connected to the second word line, a first conductive line connected to the plurality of first contact plugs, and a second conductive line connected to one of the plurality of second contact plugs.

Abstract: A power module for a vehicle, includes: a first substrate including a first metal circuit disposed on a 1-1st surface, and a first spacer extending from the first metal circuit in a first direction; a second substrate spaced from and facing the first substrate in a second direction, and including a second metal circuit disposed on a 2-1st surface facing the 1-1st surface, and a second spacer extending from the second metal circuit in the second direction; and a semiconductor chip disposed between the first substrate and the second substrate and including a power pad and a signal pad, the first spacer and the second spacer extending toward each other, and the second spacer including a 2-1st spacer connected to the power pad and a 2-2nd spacer connected to the signal pad.

Abstract: A method of operating a host device to control a storage device which includes a register is provided. The method includes: providing the storage device with a partial array refresh setting indicating a non-masking segment among a masking segment and the non-masking segment; providing a refresh command to the storage device; and providing a write command for the masking segment to the storage device to control the storage device to store data while a partial array refresh is performed in the storage device based on the refresh command.

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

Abstract: A phase-locked loop (PLL) circuit delays an input clock signal having a first frequency and generates a feedback signal to be delayed with respect to the input clock signal by one cycle. After synchronizing phases of the input clock signal and the feedback signal, a phase comparator compares the phase of the input clock signal with a phase of a reference clock signal having a second frequency, and generates a differential signal corresponding to the phase difference. A counter counts up or down in response to the differential signal. A decoder generates control signals from counting data. A voltage controlled delay line (VCDL) generates an output clock signal by delaying the input clock signal while the control signals are activated. When the phases of the input clock signal and the reference clock signal coincide with each other, the output clock signal from the VCDL has the same frequency with the input clock signal and is synchronized with the reference clock signal.

Abstract: A phase-locked loop (PLL) circuit delays an input clock signal having a first frequency and generates a feedback signal to be delayed with respect to the input clock signal by one cycle. After synchronizing phases of the input clock signal and the feedback signal, a phase comparator compares the phase of the input clock signal with a phase of a reference clock signal having a second frequency, and generates a differential signal corresponding to the phase difference. A counter counts up or down in response to the differential signal. A decoder generates control signals from counting data. A voltage controlled delay line (VCDL) generates an output clock signal by delaying the input clock signal while the control signals are activated. When the phases of the input clock signal and the reference clock signal coincide with each other, the output clock signal from the VCDL has the same frequency with the input clock signal and is synchronized with the reference clock signal.