Abstract: A drain programmed read-only memory includes a plurality of bit lines for each drain-programmed transistor. In addition, the drain-programmed read-only memory includes a pair of ground lines for each drain-programmed transistor. A decoder decodes a plurality of bits from each drain-programmed transistor by determining which bit line (if any) and which ground line is coupled to the drain-programmed transistor.

Abstract: A drain programmed read-only memory includes a plurality of bit lines for each drain-programmed transistor. In addition, the drain-programmed read-only memory includes a pair of ground lines for each drain-programmed transistor. A decoder decodes a plurality of bits from each drain-programmed transistor by determining which bit line (if any) and which ground line is coupled to the drain-programmed transistor.

Abstract: A memory includes a bitcell on a substrate, having a bitcell width and a bitcell height and a first access transistor and a second access transistor. The memory includes a first metal layer patterned to form a first pair of wordlines, including a first wordline coupled to a gate of the first access transistor and a second wordline coupled to a gate of the second access transistor. The memory includes a second metal layer patterned to form a pair of second metal layer islands. The pair of second metal layer islands include a first island coupled to the first wordline and a second island coupled to the second wordline. The memory includes a third metal layer patterned to form a pair of third metal layer interconnects, including a first interconnect coupled to the first island and a second interconnect coupled to the second island.

Abstract: A memory includes a periphery separated from one or more banks by a bitcell-to-periphery interface. The periphery includes logic circuits for the reading and writing to bitcells within the neighboring banks. Tap cells for the biasing of the periphery extend across the bitcell-to-periphery interface.

Abstract: A drain programmed read-only memory includes a plurality of bit lines for each drain-programmed transistor. In addition, the drain-programmed read-only memory includes a pair of ground lines for each drain-programmed transistor. A decoder decodes a plurality of bits from each drain-programmed transistor by determining which bit line (if any) and which ground line is coupled to the drain-programmed transistor.

Abstract: A drain programmed read-only memory includes a plurality of bit lines for each drain-programmed transistor. In addition, the drain-programmed read-only memory includes a pair of ground lines for each drain-programmed transistor. A decoder decodes a plurality of bits from each drain-programmed transistor by determining which bit line (if any) and which ground line is coupled to the drain-programmed transistor.

Abstract: A memory includes a bitcell on a substrate, having a bitcell width and a bitcell height and a first access transistor and a second access transistor. The memory includes a first metal layer patterned to form a first pair of wordlines, including a first wordline coupled to a gate of the first access transistor and a second wordline coupled to a gate of the second access transistor. The memory includes a second metal layer patterned to form a pair of second metal layer islands. The pair of second metal layer islands include a first island coupled to the first wordline and a second island coupled to the second wordline. The memory includes a third metal layer patterned to form a pair of third metal layer interconnects, including a first interconnect coupled to the first island and a second interconnect coupled to the second island.

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: A drain programmed read-only memory includes a diffusion region that spans a width of a bitcell and forms a drain of a first transistor and a second transistor. A bit line lead in a metal layer adjacent the diffusion region extends across the width of the bitcell. A first via extends from an upper half of the bit line lead and couples to a drain of the first transistor. Similarly, a second via extends from a lower half of the bit line and couples to a drain of the second transistor.

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: A drain programmed read-only memory includes a diffusion region that spans a width of a bitcell and forms a drain of a first transistor and a second transistor. A bit line lead in a metal layer adjacent the diffusion region extends across the width of the bitcell. A first via extends from an upper half of the bit line lead and couples to a drain of the first transistor. Similarly, a second via extends from a lower half of the bit line and couples to a drain of the second transistor.

Abstract: A pseudo-triple-port memory is provided that includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port including a first word line coupled to a first bit line through a first access transistor, a second read port including a second word line coupled to a second bit line through a second access transistor, and a write port including both the word lines, both the bit lines, and the pair of access transistors.

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

Abstract: A pseudo-triple-port memory is provided that includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port including a first word line coupled to a first bit line through a first access transistor, a second read port including a second word line coupled to a second bit line through a second access transistor, and a write port including both the word lines, both the bit lines, and the pair of access transistors.

Abstract: There is provided a versatile display device comprising: a first electrode layer formed on a transparent substrate; an electrochromic layer formed on the first electrode layer; a second electrode layer consisting of a plurality of first conductive line groups arranged in the first direction on the electrochromic layer; a light-emitting device layer formed on the second electrode layer and emitting light; and a third electrode layer formed on the light-emitting device layer and consisting of a plurality of second conductive line groups arranged in the second direction that is different from the first conductive line group.

Abstract: A rotor includes a rotor core which has a central portion and a circumferential portion, wherein a shaft hole is formed at the central portion, a plurality of conductor mounting holes are formed along the circumferential portion, a plurality of conductors are inserted into the conductor mounting holes, respectively, and a multiplicity of magnet mounting holes are arranged around the shaft hole along at least one radial direction from the shaft hole; and at least one permanent magnet selectively mounted into at least one corresponding magnet mounting hole.

Abstract: An oilless bearing type motor with a function of preventing oil leakage, wherein the motor includes an oilless bearing supporting a rotational shaft to be rotatable, includes a rotor of which the rotational shaft is fixed in a central portion. The rotor has an oil collecting indentation around the rotational shaft to collect oil leaked from an oilless bearing side, and is formed by pressing soft magnetic powder. Further, The oilless bearing type motor includes an oil absorption ring formed of a material absorbing a liquid to allow the oil, which moves by a centrifugal force in the oil collection indentation, to be absorbed, and installed in the oil collecting indentation.