Patents by Inventor Sung-Soo Ahn
Sung-Soo Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240132010Abstract: Disclosed are airbag integrated moving display and a control method where the airbag-integrated display includes a display movable to a forward or rearward position according to a driving mode of a vehicle, and an airbag mounted to the rear of the display and being configured to move along with a movement of the display, vary a level of inflation of the airbag based on at least one of a position of the display or a distance from a driver of the vehicle.Type: ApplicationFiled: August 16, 2023Publication date: April 25, 2024Applicant: HYUNDAI MOBIS CO., LTD.Inventors: Hyun Jun AN, Shin Jik LEE, Jun LEE, Sung Joon AHN, Ji Soo SHIN, Seok Hoon KO, Kyung Hoon KIM, Jae Seong CHA
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Patent number: 11958941Abstract: A polymer for a gel polymer electrolyte, a gel polymer electrolyte and a lithium secondary battery comprising the same are disclosed herein. In some embodiments, a polymer for the gel polymer electrolyte includes a copolymer having a main chain and a first side chain and a second side chain bonded to the main chain, wherein the main chain contains a fluoropolymer, wherein the first side chain contains a siloxane group and the second side chain contains an acrylic polymer. The polymer improves stability of a gel polymer electrolyte and a lithium secondary battery including the same.Type: GrantFiled: August 10, 2020Date of Patent: April 16, 2024Assignee: LG Energy Solution, Ltd.Inventors: Jeongae Yoon, Solji Park, Kyoung Ho Ahn, Sujeong Kim, Chul Haeng Lee, Sung Soo Yoon
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Publication number: 20240107032Abstract: The present invention relates to an image encoding and decoding technique, and more particularly, to an image encoder and decoder using unidirectional prediction. The image encoder includes a dividing unit to divide a macro block into a plurality of sub-blocks, a unidirectional application determining unit to determine whether an identical prediction mode is applied to each of the plurality of sub-blocks, and a prediction mode determining unit to determine a prediction mode with respect to each of the plurality of sub-blocks based on a determined result of the unidirectional application determining unit.Type: ApplicationFiled: December 7, 2023Publication date: March 28, 2024Applicants: Electronics and Telecommunications Research Institute, Kwangwoon University Industry-Academic Collaboration Foundation, University-Industry Cooperation Group of Kyung Hee UniversityInventors: Hae Chul CHOI, Se Yoon JEONG, Sung-Chang LIM, Jin Soo CHOI, Jin Woo HONG, Dong Gyu SIM, Seoung-Jun OH, Chang-Beom AHN, Gwang Hoon PARK, Seung Ryong KOOK, Sea-Nae PARK, Kwang-Su JEONG
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Publication number: 20240100952Abstract: Disclosed herein is a device for interlocking a display device with a vehicle, the device including a mount disposed in the vehicle, the display device being attached to and detached from the mount, a first sliding member disposed on a front surface of the mount and capable of moving forward or backward in a direction perpendicular to a rear surface of the display device, and a connector provided to the first sliding member, wherein the connector may transmit and receive electrical signals to and from the display device. The vehicle may be controlled by coupling a display device to the interlocking device disposed in the vehicle. Even when the display device is not coupled to the vehicle, the vehicle may be controlled by pairing through wireless communication between the vehicle and the display device.Type: ApplicationFiled: September 14, 2023Publication date: March 28, 2024Applicant: HYUNDAI MOBIS CO., LTD.Inventors: Shin Jik LEE, Sung Joon AHN, Ji Soo SHIN, Jun LEE, Hyun Jun AN, Seung Ho SONG
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Publication number: 20240107002Abstract: A method for coding image information includes generating prediction information by predicting information on a current coding unit, and determining whether the information on the current coding unit is the same as the prediction information. When the information on the current coding unit is the same as the prediction information, a flag indicating that the information on the current coding unit is the same as the prediction information is coded and transmitted. When the information on the current coding unit is not the same as the prediction information, a flag indicating that the information on the current coding unit is not the same as the prediction information and the information on the current coding unit are coded and transmitted.Type: ApplicationFiled: December 6, 2023Publication date: March 28, 2024Applicants: Electronics and Telecommunications Research Institute, University-Industry Cooperation Group of Kyung Hee UniversityInventors: Se Yoon JEONG, Hui Yong KIM, Sung Chang LIM, Jin Ho LEE, Ha Hyun LEE, Jong Ho KIM, Jin Soo CHOI, Jin Woong KIM, Chie Teuk AHN, Gwang Hoon PARK, Kyung Yong KIM, Tae Ryong KIM, Han Soo LEE
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Publication number: 20240073416Abstract: The present invention relates to an apparatus and method for encoding and decoding an image by skip encoding. The image-encoding method by skip encoding, which performs intra-prediction, comprises: performing a filtering operation on the signal which is reconstructed prior to an encoding object signal in an encoding object image; using the filtered reconstructed signal to generate a prediction signal for the encoding object signal; setting the generated prediction signal as a reconstruction signal for the encoding object signal; and not encoding the residual signal which can be generated on the basis of the difference between the encoding object signal and the prediction signal, thereby performing skip encoding on the encoding object signal.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicants: Electronics and Telecommunications Research Institute, Kwangwoon University Industry-Academic Collaboration Foundation, Universily-lndustry Cooperation Group of Kyung Hee UniversityInventors: Sung Chang LIM, Ha Hyun LEE, Se Yoon JEONG, Hui Yong KIM, Suk Hee CHO, Jong Ho KIM, Jin Ho LEE, Jin Soo CHOI, Jin Woong KIM, Chie Teuk AHN, Dong Gyu SIM, Seoung Jun OH, Gwang Hoon PARK, Sea Nae PARK, Chan Woong JEON
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Patent number: 11145671Abstract: A three-dimensional semiconductor memory device is provided. The memory device includes a substrate with a cell array region and a connection region adjacent to the cell array region, the connection region including a first pad region and a second pad region; an electrode structure including electrodes stacked on the substrate, the electrode structure including an upper portion forming an upper staircase structure; a first dummy structure laterally spaced apart from the upper portion of the electrode structure and provided on the first pad region; and a second dummy structure laterally spaced apart from the upper portion of the electrode structure and provided on the second pad region. Each of the first dummy structure and the second dummy structure includes a dummy staircase structure, and the first dummy structure is located at higher level than the second dummy structure.Type: GrantFiled: July 15, 2019Date of Patent: October 12, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Haejoon Lee, Sung-Soo Ahn, Ha-Na Kim
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Patent number: 11109812Abstract: An authentication apparatus includes one or more processors configured to temporally implement a neural network, used to extract a feature value from hidden nodes, that is connected to input nodes to which an electrocardiogram (ECG) signal is input so as to share a weight set with the input nodes, and to match the ECG signal and the extracted feature value to a user for registration.Type: GrantFiled: December 7, 2018Date of Patent: September 7, 2021Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and TechnologyInventors: Chisung Bae, Jin Woo Shin, Sung-Soo Ahn, Sang Joon Kim
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Patent number: 10971516Abstract: Integrated circuit devices and methods of forming the same are provided. The devices may include a substrate including a cell region and an extension region and conductive layers stacked on the cell region in a vertical direction. The conductive layers may extend onto the extension region and may have a stair-step structure on the extension region. The devices may also include vertical structures on the substrate. Each of the vertical structures may extend in the vertical direction, and the vertical structures may include a first vertical structure on the cell region and a second vertical structure on the extension region. The first vertical structure may extend through the conductive layers and may include a first channel layer, the second vertical structure may be in the stair-step structure and may include a second channel layer, and the second channel layer may be spaced apart from the substrate in the vertical direction.Type: GrantFiled: March 6, 2019Date of Patent: April 6, 2021Inventors: Sung-Soo Ahn, Yong-Hoon Son, Minhyuk Kim, Jae Ho Min, Daehyun Jang
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Patent number: 10971521Abstract: A three-dimensional semiconductor device includes: a peripheral circuit structure disposed on a lower substrate, and including an internal peripheral pad portion; an upper substrate disposed on the peripheral circuit structure; a stack structure disposed on the upper substrate, and including gate horizontal patterns; a vertical channel structure passing through the stack structure in a first region on the upper substrate; a first vertical support structure passing through the stack structure in a second region on the upper substrate; and an internal peripheral contact structure passing through the stack structure and the upper substrate, and electrically connected to the internal peripheral pad portion, wherein an upper surface of the first vertical support structure is disposed on a different level from an upper surface of the vertical channel structure, and is coplanar with an upper surface of the internal peripheral contact structure.Type: GrantFiled: September 28, 2020Date of Patent: April 6, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Han Vit Yang, Yong Hoon Son, Moon Jong Kang, Hyuk Ho Kwon, Sung Soo Ahn, So Yoon Lee
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Publication number: 20210036014Abstract: A three-dimensional semiconductor device includes: a peripheral circuit structure disposed on a lower substrate, and including an internal peripheral pad portion; an upper substrate disposed on the peripheral circuit structure; a stack structure disposed on the upper substrate, and including gate horizontal patterns; a vertical channel structure passing through the stack structure in a first region on the upper substrate; a first vertical support structure passing through the stack structure in a second region on the upper substrate; and an internal peripheral contact structure passing through the stack structure and the upper substrate, and electrically connected to the internal peripheral pad portion, wherein an upper surface of the first vertical support structure is disposed on a different level from an upper surface of the vertical channel structure, and is coplanar with an upper surface of the internal peripheral contact structure.Type: ApplicationFiled: September 28, 2020Publication date: February 4, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Han Vit YANG, Yong Hoon SON, Moon Jong KANG, Hyuk Ho KWON, Sung Soo AHN, So Yoon LEE
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Patent number: 10804289Abstract: A three-dimensional semiconductor device includes: a peripheral circuit structure disposed on a lower substrate, and including an internal peripheral pad portion; an upper substrate disposed on the peripheral circuit structure; a stack structure disposed on the upper substrate, and including gate horizontal patterns; a vertical channel structure passing through the stack structure in a first region on the upper substrate; a first vertical support structure passing through the stack structure in a second region on the upper substrate; and an internal peripheral contact structure passing through the stack structure and the upper substrate, and electrically connected to the internal peripheral pad portion, wherein an upper surface of the first vertical support structure is disposed on a different level from an upper surface of the vertical channel structure, and is coplanar with an upper surface of the internal peripheral contact structure.Type: GrantFiled: January 2, 2019Date of Patent: October 13, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Han Vit Yang, Yong Hoon Son, Moon Jong Kang, Hyuk Ho Kwon, Sung Soo Ahn, So Yoon Lee
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Publication number: 20200227434Abstract: A three-dimensional semiconductor memory device is provided. The memory device includes a substrate with a cell array region and a connection region adjacent to the cell array region, the connection region including a first pad region and a second pad region; an electrode structure including electrodes stacked on the substrate, the electrode structure including an upper portion forming an upper staircase structure; a first dummy structure laterally spaced apart from the upper portion of the electrode structure and provided on the first pad region; and a second dummy structure laterally spaced apart from the upper portion of the electrode structure and provided on the second pad region. Each of the first dummy structure and the second dummy structure includes a dummy staircase structure, and the first dummy structure is located at higher level than the second dummy structure.Type: ApplicationFiled: July 15, 2019Publication date: July 16, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Haejoon LEE, Sung-Soo AHN, Ha-Na KIM
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Publication number: 20200075627Abstract: Integrated circuit devices and methods of forming the same are provided. The devices may include a substrate including a cell region and an extension region and conductive layers stacked on the cell region in a vertical direction. The conductive layers may extend onto the extension region and may have a stair-step structure on the extension region. The devices may also include vertical structures on the substrate. Each of the vertical structures may extend in the vertical direction, and the vertical structures may include a first vertical structure on the cell region and a second vertical structure on the extension region. The first vertical structure may extend through the conductive layers and may include a first channel layer, the second vertical structure may be in the stair-step structure and may include a second channel layer, and the second channel layer may be spaced apart from the substrate in the vertical direction.Type: ApplicationFiled: March 6, 2019Publication date: March 5, 2020Inventors: SUNG-SOO AHN, YONG-HOON SON, MINHYUK KIM, JAE HO MIN, DAEHYUN JANG
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Publication number: 20200027893Abstract: A three-dimensional semiconductor device includes: a peripheral circuit structure disposed on a lower substrate, and including an internal peripheral pad portion; an upper substrate disposed on the peripheral circuit structure; a stack structure disposed on the upper substrate, and including gate horizontal patterns; a vertical channel structure passing through the stack structure in a first region on the upper substrate; a first vertical support structure passing through the stack structure in a second region on the upper substrate; and an internal peripheral contact structure passing through the stack structure and the upper substrate, and electrically connected to the internal peripheral pad portion, wherein an upper surface of the first vertical support structure is disposed on a different level from an upper surface of the vertical channel structure, and is coplanar with an upper surface of the internal peripheral contact structure.Type: ApplicationFiled: January 2, 2019Publication date: January 23, 2020Inventors: Han Vit YANG, Yong Hoon SON, Moon Jong KANG, Hyuk Ho KWON, Sung Soo AHN, So Yoon LEE
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Publication number: 20190105000Abstract: An authentication apparatus includes one or more processors configured to temporally implement a neural network, used to extract a feature value from hidden nodes, that is connected to input nodes to which an electrocardiogram (ECG) signal is input so as to share a weight set with the input nodes, and to match the ECG signal and the extracted feature value to a user for registration.Type: ApplicationFiled: December 7, 2018Publication date: April 11, 2019Applicants: SAMSUNG ELECTRONICS CO., LTD., Korea Advanced Institute of Science and TechnologyInventors: Chisung BAE, Jin Woo SHIN, Sung-Soo AHN, Sang Joon KIM
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Patent number: 10188351Abstract: An authentication apparatus includes one or more processors configured to temporally implement a neural network, used to extract a feature value from hidden nodes, that is connected to input nodes to which an electrocardiogram (ECG) signal is input so as to share a weight set with the input nodes, and to match the ECG signal and the extracted feature value to a user for registration.Type: GrantFiled: August 25, 2016Date of Patent: January 29, 2019Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and TechnologyInventors: Chisung Bae, Jin Woo Shin, Sung-Soo Ahn, Sang Joon Kim
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Patent number: 9806204Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.Type: GrantFiled: November 7, 2014Date of Patent: October 31, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Soo Ahn, O Ik Kwon, Bum-Soo Kim, Hyun-Sung Kim, Kyoung-Sub Shin, Min-Kyung Yun, Seung-Pil Chung, Won-Bong Jung
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Publication number: 20170215806Abstract: An authentication apparatus includes one or more processors configured to temporally implement a neural network, used to extract a feature value from hidden nodes, that is connected to input nodes to which an electrocardiogram (ECG) signal is input so as to share a weight set with the input nodes, and to match the ECG signal and the extracted feature value to a user for registration.Type: ApplicationFiled: August 25, 2016Publication date: August 3, 2017Applicants: SAMSUNG ELECTRONICS CO., LTD., Korea Advanced Institute of Science and TechnologyInventors: Chisung BAE, Jin Woo SHIN, Sung-Soo AHN, Sang Joon KIM
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Patent number: 9214569Abstract: According to example embodiments, a memory device includes a substrate, a channel region on the substrate, a plurality of gate electrode layers stacked on each other on the substrate, and a plurality of contact plugs. The gate electrode layers are adjacent to the channel region and extend in one direction to define a pad region. The gate electrode layers include first and second gate electrode layers. The contact plugs are connected to the gate electrode layers in the pad region. At least one of the contact plugs is electrically insulated from the from the first gate electrode layer and electrically connected to the second gate electrode layer by penetrating through the first gate electrode layer.Type: GrantFiled: August 25, 2014Date of Patent: December 15, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Ki Jeong Kim, Jung Ik Oh, Sung Soo Ahn, Dae Hyun Jang