Abstract: The present application relates to a cathode, a method of manufacturing the same, and a battery including the same. The present application may provide a cathode and a method of manufacturing the same, wherein the cathode comprises an active material layer that contains an acrylic polymer and exhibits excellent resistance to an electrolyte, excellent dispersion of its components and great adhesion to a current collector.

Abstract: A semiconductor apparatus includes a first chip that generates a first oscillator signal in response to a detection enable signal and activates a ZQ circuit in response to a ZQ enable signal, and a second chip generates the ZQ enable signal by comparing frequencies of the first oscillator signal and a second oscillator signal with each other in response to the detection enable signal.

Abstract: A pulse width compensation circuit may include a voltage control circuit and a pulse width adjustment circuit. The voltage control circuit may sense a voltage level of a first power supply voltage and generate a voltage control signal. The pulse width adjustment circuit may generate an output signal by changing a pulse width of an input signal based on the voltage control signal.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a first cell array and a second cell array, a first main word line disposed over the first cell array, a second main word line disposed over the second cell array, and a row decoder block disposed between the first cell array and the second cell array, and configured to include a common signal line that is commonly coupled to the first main word line and the second main word line such that a main word line control signal is simultaneously supplied to the first main word line and the second main word line.

Abstract: A semiconductor device includes a cell array having an upper segment and a lower segment which are classified according to refresh units. The semiconductor device includes a first repair controller configured to output a first repair signal for controlling a repair operation of the upper segment based on a fuse address, a row address, a second control signal, and selection address being at a first level, and generate a first control signal for controlling a repair operation of the lower segment based on the fuse address, the row address, and selection address.

Abstract: A semiconductor device is disclosed, which is configured to perform a test using various conditions during a test mode. The semiconductor device includes a voltage generation circuit configured to output 2n (n is an integer of n?2) bit-line precharge voltages through different power-supply lines, based on a mode control signal, and a sense amplifier configured to receive the bit-line precharge voltages from the voltage generation circuit, and supply the 2n bit-line precharge voltages to corresponding bit lines in units of 2n successive bit-lines within the same cell array.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a first cell array and a second cell array, a first main word line disposed over the first cell array, a second main word line disposed over the second cell array, and a row decoder block disposed between the first cell array and the second cell array, and configured to include a common signal line that is commonly coupled to the first main word line and the second main word line such that a main word line control signal is simultaneously supplied to the first main word line and the second main word line.

Abstract: A semiconductor apparatus includes a state storage circuit configured to store information depending on a plurality of signals, and output the stored information as a power gating signal. The semiconductor apparatus may include a power gating circuit configured to provide or block a power supply voltage to an internal operation circuit as a driving voltage in response to the power gating signal.

Abstract: A semiconductor device is disclosed, which is configured to perform a test using various conditions during a test mode. The semiconductor device includes a voltage generation circuit configured to output 2n (n is an integer of n?2) bit-line precharge voltages through different power-supply lines, based on a mode control signal, and a sense amplifier configured to receive the bit-line precharge voltages from the voltage generation circuit, and supply the 2n bit-line precharge voltages to corresponding bit lines in units of 2n successive bit-lines within the same cell array.

Abstract: A semiconductor device includes a cell array having an upper segment and a lower segment which are classified according to refresh units. The semiconductor device includes a first repair controller configured to output a first repair signal for controlling a repair operation of the upper segment based on a fuse address, a row address, a second control signal, and selection address being at a first level, and generate a first control signal for controlling a repair operation of the lower segment based on the fuse address, the row address, and selection address.

Abstract: A memory device includes a plurality of memory cells, a weak address storage block suitable for storing a weak address of a weak cell of which data retention time is shorter than a reference time, among the plurality of memory cells, a refresh counter suitable for generating a counting address, and an address selection block suitable for outputting a refresh address by selecting one of the counting address and the weak address, wherein, in selecting the counting address, the address selection block selects the weak address for a predetermined period, when a value of at least one preset bit of the counting address is changed.

Abstract: A semiconductor apparatus includes a first chip that generates a first oscillator signal in response to a detection enable signal and activates a ZQ circuit in response to a ZQ enable signal, and a second chip generates the ZQ enable signal by comparing frequencies of the first oscillator signal and a second oscillator signal with each other in response to the detection enable signal.

Abstract: A pulse width compensation circuit may include a voltage control circuit and a pulse width adjustment circuit. The voltage control circuit may sense a voltage level of a first power supply voltage and generate a voltage control signal. The pulse width adjustment circuit may generate an output signal by changing a pulse width of an input signal based on the voltage control signal.

Abstract: A semiconductor apparatus includes a state storage circuit configured to store information depending on a plurality of signals, and output the stored information as a power gating signal. The semiconductor apparatus may include a power gating circuit configured to provide or block a power supply voltage to an internal operation circuit as a driving voltage in response to the power gating signal.

Abstract: The semiconductor device may include a driving voltage supply unit configured to supply a voltage such that a main word line signal has the voltage. The semiconductor device may include a current path control unit configured to increase the speed at which the voltage of the main word line signal decreases.

Abstract: A memory device may include: a plurality of memory cells; a weak cell information storage unit suitable for storing a weak address and parity information corresponding to one or more weak cells having a shorter data retention time than a reference time, among the plurality of memory cells; an ECC (Error Correction Code) circuit suitable for detecting and correcting an error bit of the one or more weak cells using the parity information; and a refresh control unit suitable for controlling the plurality of memory cells to be refreshed at a cycle equal to or more than the reference time.

Abstract: A test device includes: a test control unit suitable for detecting a deterioration-expected unit circuit among a plurality of unit circuits included in a test-subject device according to operation histories of the plural unit circuits, and detecting a deterioration degree according to a test output value of the deterioration-expected unit circuit; and an interface unit suitable for routing control operation results and test results between the test control unit and the test-subject device during a test operation.

Abstract: A semiconductor device may be provided. The semiconductor device may be configured for detecting a defect of a fuse set. The semiconductor device may include a pseudo initial signal generator configured to generate pseudo initial information on the basis of a test mode signal. The semiconductor device may include a fuse-set defect detector configured to compare fuse-set information of a fuse set or the pseudo initial information with a reference value on the basis of a fuse-set address, and detect a defect of the fuse set.

Abstract: A test device includes: a test control unit suitable for detecting a deterioration-expected unit circuit among a plurality of unit circuits included in a test-subject device according to operation histories of the plural unit circuits, and detecting a deterioration degree according to a test output value of the deterioration-expected unit circuit; and an interface unit suitable for routing control operation results and test results between the test control unit and the test-subject device during a test operation.

Abstract: A semiconductor memory device including a weak cell storage circuit suitable for programming therein weak cell information, and outputting the weak cell information in an initialization operation; a cell array region including a first cell region which stores the weak cell information received from the weak cell storage circuit, in the initialization operation; a refresh address generation block suitable for generating a refresh address by counting a refresh signal, and outputting a weak cell address corresponding to the weak cell information outputted from the first cell region, as the refresh address, with a predetermined cycle; and a refresh circuit suitable for performing a refresh operation for a word line corresponding to the refresh address, among a plurality of word lines.