Abstract: A method and apparatus for transmitting/receiving data in a communication system are provided, in which an MCS level is determined for data, a codeword including the data and a parity is generated by encoding the data using the determined MCS level, code symbols are generated from the codeword using IR scheme, and each of the code symbols is sent in a corresponding subframe.

Abstract: A method and apparatus for transmitting/receiving data in a communication system are provided, in which an MCS level is determined for data, a codeword including the data and a parity is generated by encoding the data using the determined MCS level, code symbols are generated from the codeword using IR scheme, and each of the code symbols is sent in a corresponding subframe.

Abstract: Provided is an apparatus and method for communicating data in a hybrid diversity mode in a broadband wireless communication system. In a method for transmitting data to a subscriber station (SS) in the broadband wireless communication system, null subbands are determined using feedback information received from the SS. TX data to be transmitted to the SS are mapped to a diversity zone from which the null subbands has been excluded. The mapped data are OFDM-modulated and transmitted to the SS. In this way, frequency subbands with poor channel conditions are excluded from data transmission. Accordingly, it is possible to enhance the FER performance and transmit data at a high MCS level.

Abstract: A signal transmission/transmission apparatus and method in a communication system are provided, in which a BS groups MSs serviced by the BS into MS groups and allocates a DL dedicated channel and a UL dedicated channel to each of the MS groups.

Abstract: A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.

Abstract: A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.

Abstract: A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.

Abstract: A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.

Abstract: An integrated circuit contains a central processing unit (“CPU”), a graphic control hub (“GCH”), a memory control hub (“MCH”), and a phase lock loop (“PLL”). The GCH, MCH, and PLL are coupled to the CPU. The MCH controls memory transactions. The PLL is configured to allow the CPU to operate at more than one power consumption states.

Abstract: A system includes a portable computer having a first bus and a docking base having a second bus. A serial link (e.g., a 1394 link) couples the portable computer to the docking base. The portable computer may include a controller to convert a first bus cycle targeted for the second bus to a serial cycle. The first and second buses may each include a Peripheral Component Interconnect (PCI) bus.

Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic.

Abstract: A method and apparatus for stopping a bus clock when there are no activities present on a bus. In the illustrated embodiment, an AGP bus couples a graphics controller to core logic to transfer data between the two devices. A controller generates a first (AGP bus) clock signal CLK and a second (internal) clock signal iclk for the first and second devices. If the controller determines that there are no graphics activities on the AGP bus (i.e., the bus is idle), the controller issues a stop request to stop the internal clock signal iclk. The processing of the stop request is delayed for a period of seven cycles on the AGP bus clock CLK to await for an objection from either the graphics controller or the core logic. If an objection is received during the seven cycle delay, the internal clock iclk will not be stopped, and will continue to run. However, if an objection is not received, then the internal clock iclk will stop.

Abstract: A method and apparatus for indicating when a device in a computer system is communicating with memory. Information is communicated between the device and memory in a manner that bypasses a bus. A side-band signal that indicates that this communication is transpiring is sent to a second device connected to the second bus. In response to this side-band signal, a bit in a register of the second device is set to a value that is then communicated by way of the second bus.

Abstract: The present invention provides a method and apparatus for splitting a bus target response between two devices in a computer system. In one embodiment, the computer system includes a bus having a first signal line and a second signal line, a third signal line, and two agents coupled to the bus and the third signal line. The first agent claims to be a target of a transaction on the bus without decoding the address associated with the transaction by asserting the first signal on the first signal line. The second agent responds to the transaction as the target. The second agent thereafter asserts a third signal on the third signal line to coordinate deassertion of the first signal on the first signal line by the first agent and concurrent assertion of the second signal on the second signal line by the second agent.

Abstract: Prior art quiet docking and undocking methods used an interface that was located within the notebook computer, thus adding to the complexity, weight, and power consumption of the notebook computer. The present invention provides for a method for quiet docking and undocking of a notebook computer using interface circuitry located within the docking station. Moreover, the method of the present invention provides for docking and undocking whether the notebook computer is in a powered-on or suspend mode. The notebook computer is docked and undocked to the docking station such that any transaction occurring on the system bus during the docking/undocking sequence is not affected.

Abstract: Prior art quiet docking and undocking methods used an interface that was located within the notebook computer, thus adding to the cost, complexity, weight, and power consumption of the notebook computer. The present invention provides for an apparatus for quiet docking of a notebook computer to a docking station, including interface circuitry located within the docking station. The interface detects when the notebook computer has been inserted within the docking station, and correspondingly enables a switch such that a common system bus is coupled between the notebook computer and the docking station. The interface also generates events to allow a software routine to configure the notebook computer and docking station without prior user intervention. The interface also includes circuitry to detect an undock request, and correspondingly undock the computer such that a transaction occurring on the system bus is not affected.

Abstract: A computer system that implements a direct memory access (DMA) request passing protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. The PCI bus is coupled to at least one DMA agent and a DMA controller. The DMA agent issues DMA requests to the DMA controller using the electrical interface of the PCI bus. According to one embodiment, a system I/O controller receives the DMA requests and passes them on to the DMA controller, which arbitrates the DMA requests and passes back a grant to the system I/O controller. The system I/O controller uses the electrical interface of the PCI bus to pass the grant to the DMA agent. The same DMA request passing protocol may be implemented in any bus having an electrical interface that specifies a unique request signal line for each bus agent of the bus.

Abstract: A circuit for selectively invoking a particular interrupt service routine to handle a particular interrupt request. The present invention includes a programmable register with one or more bits per interrupt request input. The present invention also includes interrupt selection logic which outputs a particular interrupt in response to an interrupt request input and data stored in the programmable register. The interrupt then invokes the associated interrupt service routine to handle the interrupt request. The present invention is used to choose the interrupt service routine to handle a particular interrupt request from any source within the computer system in any computer system operating mode.

Abstract: A system having a portable computer, a docking station and an interface coupled between the portable computer and the docking station that is responsive to unpreconditioned insertion or removal of the portable computer into or from the docking station respectively. When the portable computer is being inserted into or removed from the docking station, the interface generates events to allow software to configure (e.g., precondition) the portable computer and the docking station without prior user intervention.

Abstract: A computer system has a first bus, a first bus bridge, and a second bus bridge. The first bridge connects the first bus to a second bus and the second bridge connects the first bus to a third bus. Normally, the first bridge behaves as the only subtractive decode agent on the first bus, claiming all transactions initiated on the first bus that target agents on the second bus or the third bus. If the first bridge claims a transaction targetting an agent on the third bus, the first bridge transfers the responsibility to respond to the transaction to the second bridge. The first bridge does not behave as the subtractive decode agent on the first bus when transactions are initiated on the second bus and forwarded to the first bus. In that case, the second bridge behaves as the subtractive decode agent on the first bus.